2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include <fx2macros.h>
27 #include <gpif-acquisition.h>
29 enum gpif_status gpif_acquiring = STOPPED;
31 static void gpif_reset_waveforms(void)
39 for (i = 0; i < 128; i++)
43 static void gpif_setup_registers(void)
45 /* TODO. Value probably irrelevant, as we don't use RDY* signals? */
48 /* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
51 /* When GPIF is idle, tri-state the data bus. */
52 /* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
53 GPIFIDLECS = (0 << 0);
55 /* When GPIF is idle, set CTL0-CTL5 to 0. */
59 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
62 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
63 * [3:2] = FIFOWR index, [1:0] = FIFORD index
65 GPIFWFSELECT = (0x3u << 6) | (0x2u << 4) | (0x1u << 2) | (0x0u << 0);
67 /* Contains RDY* pin values. Read-only according to TRM. */
70 /* Make GPIF stop on transaction count not flag. */
71 EP2GPIFPFSTOP = (0 << 0);
74 static void gpif_init_addr_pins(void)
77 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
78 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
79 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
81 PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
82 OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
83 PORTECFG |= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
84 OEE |= 0x80; /* Configure PORTE[7] as output. */
86 GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
88 GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
91 static void gpif_init_flowstates(void)
93 /* Clear all flowstate registers, we don't use this functionality. */
104 void gpif_init_la(void)
107 * Setup the FX2 in GPIF master mode, using the internal clock
108 * (non-inverted) at 48MHz, and using async sampling.
112 /* Abort currently executing GPIF waveform (if any). */
115 /* Setup the GPIF registers. */
116 gpif_setup_registers();
118 /* Reset WAVEDATA. */
119 gpif_reset_waveforms();
121 /* Initialize GPIF address pins, output initial values. */
122 gpif_init_addr_pins();
124 /* Initialize flowstate registers (not used by us). */
125 gpif_init_flowstates();
127 /* Reset the status. */
128 gpif_acquiring = STOPPED;
131 static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
135 * Delay cmd->sample_delay clocks.
141 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
158 static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
162 * Branch to IDLE if condition is true, back to S0 otherwise.
164 pSTATE[0] = (7 << 3) | (0 << 0);
168 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
170 pSTATE[8] = (1 << 1) | (1 << 0);
180 * Evaluate if the FIFO full flag is set.
181 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
183 pSTATE[24] = (6 << 3) | (6 << 0);
186 bool gpif_acquisition_prepare(const struct cmd_start_acquisition *cmd)
189 volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
191 /* Ensure GPIF is idle before reconfiguration. */
192 while (!(GPIFTRIG & 0x80));
194 /* Configure the EP2 FIFO. */
195 if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
196 EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
198 EP2FIFOCFG = bmAUTOIN;
201 /* Set IFCONFIG to the correct clock source. */
202 if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
203 IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
206 IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
210 /* Populate delay states. */
211 if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
212 cmd->sample_delay_h >= 6)
215 if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
216 uint8_t delay_1, delay_2 = cmd->sample_delay_l;
218 /* We need a pulse where the CTL1/2 pins alternate states. */
219 if (cmd->sample_delay_h) {
220 for (i = 0; i < cmd->sample_delay_h; i++)
221 gpif_make_delay_state(pSTATE++, 0, 0x06);
223 delay_1 = delay_2 / 2;
225 gpif_make_delay_state(pSTATE++, delay_1, 0x06);
228 /* sample_delay_l is always != 0 for the supported rates. */
229 gpif_make_delay_state(pSTATE++, delay_2, 0x00);
231 for (i = 0; i < cmd->sample_delay_h; i++)
232 gpif_make_delay_state(pSTATE++, 0, 0x00);
234 if (cmd->sample_delay_l != 0)
235 gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
238 /* Populate S1 - the decision point. */
239 gpif_make_data_dp_state(pSTATE++);
241 /* Update the status. */
242 gpif_acquiring = PREPARED;
247 void gpif_acquisition_start(void)
249 /* Execute the whole GPIF waveform once. */
252 /* Perform the initial GPIF read. */
253 gpif_fifo_read(GPIF_EP2);
255 /* Update the status. */
256 gpif_acquiring = RUNNING;
261 /* Detect if acquisition has completed. */
262 if ((gpif_acquiring == RUNNING) && (GPIFTRIG & 0x80)) {
263 /* Activate NAK-ALL to avoid race conditions. */
267 /* Switch to manual mode. */
275 /* Return to auto mode. */
276 EP2FIFOCFG = bmAUTOIN;
279 /* Release NAK-ALL. */
283 gpif_acquiring = STOPPED;