]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * This file is part of the fx2lafw project. | |
3 | * | |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
21 | /* | |
22 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
23 | * | |
24 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
25 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
26 | * | |
27 | * Technical notes: | |
28 | * | |
29 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
30 | * - We use the internal 48MHz clock for GPIF. | |
31 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7. | |
32 | * Support for 16 channels is not yet included, but might be added later. | |
33 | * - Endpoint 2 is used for data transfers from FX2 to host. | |
34 | * - The endpoint is quad-buffered. | |
35 | * | |
36 | * Documentation: | |
37 | * | |
38 | * - See http://sigrok.org/wiki/Fx2lafw | |
39 | */ | |
40 | ||
41 | #include <fx2regs.h> | |
42 | #include <fx2macros.h> | |
43 | #include <delay.h> | |
44 | #include <setupdat.h> | |
45 | #include <eputils.h> | |
46 | #include <gpif.h> | |
47 | ||
48 | #include <command.h> | |
49 | #include <fx2lafw.h> | |
50 | #include <gpif-acquisition.h> | |
51 | ||
52 | /* ... */ | |
53 | volatile bit got_sud; | |
54 | BYTE vendor_command; | |
55 | ||
56 | static void setup_endpoints(void) | |
57 | { | |
58 | /* Setup EP2 (IN). */ | |
59 | EP2CFG = (1 << 7) | /* EP is valid/activated */ | |
60 | (1 << 6) | /* EP direction: IN */ | |
61 | (1 << 5) | (0 << 4) | /* EP Type: bulk */ | |
62 | (1 << 3) | /* EP buffer size: 1024 */ | |
63 | (0 << 2) | /* Reserved. */ | |
64 | (0 << 1) | (0 << 0); /* EP buffering: quad buffering */ | |
65 | SYNCDELAY(); | |
66 | ||
67 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ | |
68 | EP1INCFG &= ~bmVALID; | |
69 | SYNCDELAY(); | |
70 | EP1OUTCFG &= ~bmVALID; | |
71 | SYNCDELAY(); | |
72 | EP4CFG &= ~bmVALID; | |
73 | SYNCDELAY(); | |
74 | EP6CFG &= ~bmVALID; | |
75 | SYNCDELAY(); | |
76 | EP8CFG &= ~bmVALID; | |
77 | SYNCDELAY(); | |
78 | ||
79 | /* EP2: Reset the FIFOs. */ | |
80 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
81 | RESETFIFO(0x02) | |
82 | ||
83 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ | |
84 | EP2FIFOCFG = bmAUTOIN; | |
85 | SYNCDELAY(); | |
86 | ||
87 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
88 | EP2AUTOINLENH = 0x02; | |
89 | SYNCDELAY(); | |
90 | EP2AUTOINLENL = 0x00; | |
91 | SYNCDELAY(); | |
92 | ||
93 | /* EP2: Set the GPIF flag to 'full'. */ | |
94 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); | |
95 | SYNCDELAY(); | |
96 | } | |
97 | ||
98 | static void send_fw_version(void) | |
99 | { | |
100 | /* Populate the buffer */ | |
101 | struct version_info *const vi = (struct version_info*)EP0BUF; | |
102 | vi->major = FX2LAFW_VERSION_MAJOR; | |
103 | vi->minor = FX2LAFW_VERSION_MINOR; | |
104 | ||
105 | /* Send the message */ | |
106 | EP0BCH = 0; | |
107 | EP0BCL = sizeof(struct version_info); | |
108 | } | |
109 | ||
110 | BOOL handle_vendorcommand(BYTE cmd) | |
111 | { | |
112 | /* Protocol implementation */ | |
113 | switch (cmd) { | |
114 | case CMD_START: | |
115 | vendor_command = cmd; | |
116 | EP0BCL = 0; | |
117 | return TRUE; | |
118 | ||
119 | case CMD_GET_FW_VERSION: | |
120 | send_fw_version(); | |
121 | return TRUE; | |
122 | } | |
123 | ||
124 | return FALSE; | |
125 | } | |
126 | ||
127 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
128 | { | |
129 | /* We only support interface 0, alternate interface 0. */ | |
130 | if (ifc != 0) | |
131 | return FALSE; | |
132 | ||
133 | *alt_ifc = 0; | |
134 | return TRUE; | |
135 | } | |
136 | ||
137 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
138 | { | |
139 | /* We only support interface 0, alternate interface 0. */ | |
140 | if (ifc != 0 || alt_ifc != 0) | |
141 | return FALSE; | |
142 | ||
143 | /* Perform procedure from TRM, section 2.3.7: */ | |
144 | ||
145 | /* (1) TODO. */ | |
146 | ||
147 | /* (2) Reset data toggles of the EPs in the interface. */ | |
148 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
149 | RESETTOGGLE(0x82); | |
150 | #ifdef DEBUG | |
151 | RESETTOGGLE(0x86); | |
152 | #endif | |
153 | ||
154 | /* (3) Restore EPs to their default conditions. */ | |
155 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
156 | RESETFIFO(0x02); | |
157 | /* TODO */ | |
158 | #ifdef DEBUG | |
159 | RESETFIFO(0x06); | |
160 | #endif | |
161 | ||
162 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ | |
163 | ||
164 | return TRUE; | |
165 | } | |
166 | ||
167 | BYTE handle_get_configuration(void) | |
168 | { | |
169 | /* We only support configuration 1. */ | |
170 | return 1; | |
171 | } | |
172 | ||
173 | BOOL handle_set_configuration(BYTE cfg) | |
174 | { | |
175 | /* We only support configuration 1. */ | |
176 | return (cfg == 1) ? TRUE : FALSE; | |
177 | } | |
178 | ||
179 | void sudav_isr(void) interrupt SUDAV_ISR | |
180 | { | |
181 | got_sud = TRUE; | |
182 | CLEAR_SUDAV(); | |
183 | } | |
184 | ||
185 | void sof_isr(void) interrupt SOF_ISR using 1 | |
186 | { | |
187 | CLEAR_SOF(); | |
188 | } | |
189 | ||
190 | void usbreset_isr(void) interrupt USBRESET_ISR | |
191 | { | |
192 | handle_hispeed(FALSE); | |
193 | CLEAR_USBRESET(); | |
194 | } | |
195 | ||
196 | void hispeed_isr(void) interrupt HISPEED_ISR | |
197 | { | |
198 | handle_hispeed(TRUE); | |
199 | CLEAR_HISPEED(); | |
200 | } | |
201 | ||
202 | void fx2lafw_init(void) | |
203 | { | |
204 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
205 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; | |
206 | ||
207 | got_sud = FALSE; | |
208 | vendor_command = 0; | |
209 | ||
210 | /* Renumerate. */ | |
211 | RENUMERATE_UNCOND(); | |
212 | ||
213 | SETCPUFREQ(CLK_48M); | |
214 | ||
215 | USE_USB_INTS(); | |
216 | ||
217 | /* TODO: Does the order of the following lines matter? */ | |
218 | ENABLE_SUDAV(); | |
219 | ENABLE_SOF(); | |
220 | ENABLE_HISPEED(); | |
221 | ENABLE_USBRESET(); | |
222 | ||
223 | /* Global (8051) interrupt enable. */ | |
224 | EA = 1; | |
225 | ||
226 | /* Setup the endpoints. */ | |
227 | setup_endpoints(); | |
228 | ||
229 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
230 | gpif_init_la(); | |
231 | } | |
232 | ||
233 | void fx2lafw_poll(void) | |
234 | { | |
235 | if (got_sud) { | |
236 | handle_setupdata(); | |
237 | got_sud = FALSE; | |
238 | } | |
239 | ||
240 | if (vendor_command) { | |
241 | switch (vendor_command) { | |
242 | case CMD_START: | |
243 | if((EP0CS & bmEPBUSY) != 0) | |
244 | break; | |
245 | ||
246 | if(EP0BCL == 2) { | |
247 | gpif_acquisition_start( | |
248 | (const struct cmd_start_acquisition*)EP0BUF); | |
249 | } | |
250 | ||
251 | /* Acknowledge the vendor command. */ | |
252 | vendor_command = 0; | |
253 | break; | |
254 | ||
255 | default: | |
256 | /* Unimplemented command. */ | |
257 | vendor_command = 0; | |
258 | break; | |
259 | } | |
260 | } | |
261 | ||
262 | gpif_poll(); | |
263 | } | |
264 | ||
265 | void main(void) | |
266 | { | |
267 | fx2lafw_init(); | |
268 | while (1) | |
269 | fx2lafw_poll(); | |
270 | } |