[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	IOE = IOE^0x04;
	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 15,    1,   0, 2, 1, 0x40, 0xaa },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{ 11,    1,   1, 2, 0, 0x40, 0xaa },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  6,    2,   2, 2, 0, 0x40, 0xaa },
	{  5,    3,   2, 2, 0, 0x40, 0xaa },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  3,    5,   4, 2, 0, 0x40, 0xaa },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		set_calibration_pulse(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTCCFG = 0;
	PORTACFG = 0;
	PORTECFG = 0;
	OEE = 0xFF;
	OEC = 0xff;
	OEA = 0x80;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
ce1d0a86 BL	29	/* Change to support as many interfaces as you need. */
	30	static BYTE altiface = 0;
	31
	32	static volatile __bit dosud = FALSE;
	33	static volatile __bit dosuspend = FALSE;
	34
	35	extern __code BYTE highspd_dscr;
	36	extern __code BYTE fullspd_dscr;
	37
	38	void resume_isr(void) __interrupt RESUME_ISR
	39	{
	40	CLEAR_RESUME();
	41	}
	42
	43	void sudav_isr(void) __interrupt SUDAV_ISR
	44	{
	45	dosud = TRUE;
	46	CLEAR_SUDAV();
	47	}
	48
	49	void usbreset_isr(void) __interrupt USBRESET_ISR
	50	{
	51	handle_hispeed(FALSE);
	52	CLEAR_USBRESET();
	53	}
	54
	55	void hispeed_isr(void) __interrupt HISPEED_ISR
	56	{
	57	handle_hispeed(TRUE);
	58	CLEAR_HISPEED();
	59	}
	60
	61	void suspend_isr(void) __interrupt SUSPEND_ISR
	62	{
	63	dosuspend = TRUE;
	64	CLEAR_SUSPEND();
	65	}
	66
	67	void timer2_isr(void) __interrupt TF2_ISR
	68	{
3968bbfb	69	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
ce1d0a86 BL	70	IOE = IOE^0x04;
	71	TF2 = 0;
	72	}
	73
	74	/**
3968bbfb UH	75	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	76	* (attentuator). The second stage is then doing the gain by 3 different
	77	* resistor values switched into the feedback loop.
	78	*
ce1d0a86 BL	79	* #Channel 0:
	80	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	81	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	82	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	83	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	84	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	85	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	86	*
ce1d0a86 BL	87	* #Channel 1:
	88	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	89	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	90	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	91	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	92	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	93	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	94	*/
	95	static BOOL set_voltage(BYTE channel, BYTE val)
	96	{
	97	BYTE bits_C, bit_E, mask_C, mask_E;
	98
	99	if (channel == 0) {
	100	mask_C = 0x0E;
	101	mask_E = 0x00;
	102	bit_E = 0;
	103	switch (val) {
	104	case 1:
	105	bits_C = 0x02;
	106	break;
	107	case 2:
	108	bits_C = 0x06;
	109	break;
	110	case 5:
	111	bits_C = 0x00;
	112	break;
	113	case 10:
	114	bits_C = 0x04;
	115	break;
	116	case 20:
	117	bits_C = 0x08;
	118	break;
	119	default:
	120	return FALSE;
	121	}
	122	} else if (channel == 1) {
	123	mask_C = 0x30;
	124	mask_E = 0x02;
	125	switch (val) {
	126	case 1:
	127	bits_C = 0x00;
	128	bit_E = 0x02;
	129	break;
	130	case 2:
	131	bits_C = 0x10;
	132	bit_E = 0x02;
	133	break;
	134	case 5:
	135	bits_C = 0x00;
	136	bit_E = 0x00;
	137	break;
	138	case 10:
	139	bits_C = 0x10;
	140	bit_E = 0x00;
	141	break;
	142	case 20:
	143	bits_C = 0x20;
	144	bit_E = 0x00;
	145	break;
	146	default:
	147	return FALSE;
	148	}
	149	} else {
	150	return FALSE;
151	}
152	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
153	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
154
155	return TRUE;
156	}
157
75ad0fa5 BL	158	/**
	159	* Each LSB in the nibble of the byte controls the coupling per channel.
	160	*
	161	* Setting PE3 disables AC coupling capacitor on CH0.
	162	* Setting PE0 disables AC coupling capacitor on CH1.
	163	*/
	164	static void set_coupling(BYTE coupling_cfg)
	165	{
	166	if (coupling_cfg & 0x01)
	167	IOE \|= 0x08;
	168	else
	169	IOE &= ~0x08;
	170
	171	if (coupling_cfg & 0x10)
	172	IOE \|= 0x01;
	173	else
	174	IOE &= ~0x01;
	175	}
	176
ce1d0a86 BL	177	static BOOL set_numchannels(BYTE numchannels)
	178	{
	179	if (numchannels == 1 \|\| numchannels == 2) {
	180	BYTE fifocfg = 7 + numchannels;
	181	EP2FIFOCFG = fifocfg;
	182	EP6FIFOCFG = fifocfg;
	183	return TRUE;
	184	}
	185
	186	return FALSE;
	187	}
	188
	189	static void clear_fifo(void)
	190	{
	191	GPIFABORT = 0xff;
	192	SYNCDELAY3;
	193	FIFORESET = 0x80;
	194	SYNCDELAY3;
	195	FIFORESET = 0x82;
	196	SYNCDELAY3;
	197	FIFORESET = 0x86;
	198	SYNCDELAY3;
	199	FIFORESET = 0;
	200	}
	201
	202	static void stop_sampling(void)
	203	{
	204	GPIFABORT = 0xff;
	205	SYNCDELAY3;
	206	INPKTEND = (altiface == 0) ? 6 : 2;
	207	}
	208
	209	static void start_sampling(void)
	210	{
	211	int i;
	212
be6d306d UH	213	SET_ANALOG_MODE();
be6d306d UH	214
ce1d0a86 BL	215	clear_fifo();
	216
	217	for (i = 0; i < 1000; i++);
	218
	219	while (!(GPIFTRIG & 0x80))
	220	;
	221
	222	SYNCDELAY3;
	223	GPIFTCB1 = 0x28;
	224	SYNCDELAY3;
	225	GPIFTCB0 = 0;
	226	GPIFTRIG = (altiface == 0) ? 6 : 4;
	227
	228	}
	229
	230	static void select_interface(BYTE alt)
	231	{
	232	const BYTE *pPacketSize = \
	233	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	234	+ (9 + (16 * alt) + 9 + 4);
	235
	236	altiface = alt;
	237
	238	if (alt == 0) {
	239	/* Bulk on EP6. */
	240	EP2CFG = 0x00;
	241	EP6CFG = 0xe0;
	242	EP6GPIFFLGSEL = 1;
	243	EP6AUTOINLENL = pPacketSize[0];
	244	EP6AUTOINLENH = pPacketSize[1];
	245	} else {
	246	/* Iso on EP2. */
	247	EP2CFG = 0xd8;
	248	EP6CFG = 0x00;
	249	EP2GPIFFLGSEL = 1;
	250	EP2AUTOINLENL = pPacketSize[0];
	251	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	252	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	253	}
	254	}
	255
	256	static const struct samplerate_info {
	257	BYTE rate;
	258	BYTE wait0;
	259	BYTE wait1;
	260	BYTE opc0;
	261	BYTE opc1;
	262	BYTE out0;
	263	BYTE ifcfg;
	264	} samplerates[] = {
	265	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	266	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	267	{ 24, 1, 0, 2, 1, 0x40, 0xea },
	268	{ 16, 1, 1, 2, 0, 0x40, 0xea },
33c275bb	269	{ 15, 1, 0, 2, 1, 0x40, 0xaa },
ce1d0a86	270	{ 12, 2, 1, 2, 0, 0x40, 0xea },
33c275bb	271	{ 11, 1, 1, 2, 0, 0x40, 0xaa },
ce1d0a86	272	{ 8, 3, 2, 2, 0, 0x40, 0xea },
33c275bb BL	273	{ 6, 2, 2, 2, 0, 0x40, 0xaa },
33c275bb BL	274	{ 5, 3, 2, 2, 0, 0x40, 0xaa },
ce1d0a86	275	{ 4, 6, 5, 2, 0, 0x40, 0xea },
33c275bb	276	{ 3, 5, 4, 2, 0, 0x40, 0xaa },
ce1d0a86 BL	277	{ 2, 12, 11, 2, 0, 0x40, 0xea },
	278	{ 1, 24, 23, 2, 0, 0x40, 0xea },
	279	{ 50, 48, 47, 2, 0, 0x40, 0xea },
	280	{ 20, 120, 119, 2, 0, 0x40, 0xea },
	281	{ 10, 240, 239, 2, 0, 0x40, 0xea },
	282	};
	283
	284	static BOOL set_samplerate(BYTE rate)
	285	{
	286	BYTE i = 0;
	287
	288	while (samplerates[i].rate != rate) {
	289	i++;
	290	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	291	return FALSE;
	292	}
	293
	294	IFCONFIG = samplerates[i].ifcfg;
	295
	296	AUTOPTRSETUP = 7;
24373950	297	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	298	AUTOPTRL2 = 0x00;
	299
	300	/*
	301	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	302	* wait 24, CTLx=0, FIFO
	303	* wait 23, CTLx=1
	304	* jump 0, CTLx=1
ce1d0a86 BL	305	*
ce1d0a86 BL	306	* The program for 24 MHz is:
3968bbfb UH	307	* wait 1, CTLx=0, FIFO
3968bbfb UH	308	* jump 0, CTLx=1
ce1d0a86 BL	309	*
ce1d0a86 BL	310	* The program for 30/48 MHz is:
3968bbfb UH	311	* jump 0, CTLx=Z, FIFO, LOOP
	312	*
	313	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	314	*/
ce1d0a86 BL	315
24373950	316	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	317	EXTAUTODAT2 = samplerates[i].wait0;
	318	EXTAUTODAT2 = samplerates[i].wait1;
	319	EXTAUTODAT2 = 1;
	320	EXTAUTODAT2 = 0;
	321	EXTAUTODAT2 = 0;
	322	EXTAUTODAT2 = 0;
	323	EXTAUTODAT2 = 0;
	324	EXTAUTODAT2 = 0;
	325
24373950	326	/* OPCODE 0-7 */
ce1d0a86 BL	327	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	328	EXTAUTODAT2 = samplerates[i].opc1;
24373950	329	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	330	EXTAUTODAT2 = 0;
	331	EXTAUTODAT2 = 0;
	332	EXTAUTODAT2 = 0;
	333	EXTAUTODAT2 = 0;
	334	EXTAUTODAT2 = 0;
	335
24373950	336	/* OUTPUT 0-7 */
ce1d0a86	337	EXTAUTODAT2 = samplerates[i].out0;
3968bbfb UH	338	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
3968bbfb UH	339	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	340	EXTAUTODAT2 = 0;
	341	EXTAUTODAT2 = 0;
	342	EXTAUTODAT2 = 0;
	343	EXTAUTODAT2 = 0;
	344	EXTAUTODAT2 = 0;
ce1d0a86	345
24373950	346	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	347	EXTAUTODAT2 = 0;
	348	EXTAUTODAT2 = 0;
	349	EXTAUTODAT2 = 0;
	350	EXTAUTODAT2 = 0;
	351	EXTAUTODAT2 = 0;
	352	EXTAUTODAT2 = 0;
	353	EXTAUTODAT2 = 0;
	354	EXTAUTODAT2 = 0;
	355
	356	for (i = 0; i < 96; i++)
	357	EXTAUTODAT2 = 0;
	358
	359	return TRUE;
	360	}
	361
a425fae9 BL	362	static BOOL set_calibration_pulse(BYTE fs)
	363	{
	364	switch (fs) {
	365	case 0: // 100Hz
	366	RCAP2L = -10000 & 0xff;
386296a7	367	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	368	return TRUE;
	369	case 1: // 1kHz
	370	RCAP2L = -1000 & 0xff;
386296a7	371	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	372	return TRUE;
a425fae9 BL	373	case 10: // 1kHz
386296a7	374	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	375	RCAP2H = 0xff;
	376	return TRUE;
	377	case 50: // 50kHz
386296a7	378	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	379	RCAP2H = 0xff;
	380	return TRUE;
	381	default:
	382	return FALSE;
	383	}
	384	}
	385
ce1d0a86 BL	386	/* Set alt_ifc to the current alt interface for ifc. /
	387	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	388	{
	389	(void)ifc;
	390
	391	*alt_ifc = altiface;
	392
	393	return TRUE;
	394	}
	395
	396	/*
	397	* Return TRUE if you set the interface requested.
	398	*
	399	* Note: This function should reconfigure and reset the endpoints
	400	* according to the interface descriptors you provided.
	401	*/
	402	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	403	{
	404	if (ifc == 0)
	405	select_interface(alt_ifc);
	406
	407	return TRUE;
	408	}
	409
	410	BYTE handle_get_configuration(void)
	411	{
	412	/* We only support configuration 0. */
	413	return 0;
	414	}
	415
	416	BOOL handle_set_configuration(BYTE cfg)
	417	{
	418	/* We only support configuration 0. */
	419	(void)cfg;
	420
	421	return TRUE;
	422	}
	423
	424	BOOL handle_vendorcommand(BYTE cmd)
	425	{
	426	stop_sampling();
	427
	428	/* Clear EP0BCH/L for each valid command. */
a425fae9	429	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	430	EP0BCH = 0;
	431	EP0BCL = 0;
	432	while (EP0CS & bmEPBUSY);
	433	}
	434
	435	switch (cmd) {
	436	case 0xe0:
	437	case 0xe1:
	438	set_voltage(cmd - 0xe0, EP0BUF[0]);
	439	return TRUE;
	440	case 0xe2:
	441	set_samplerate(EP0BUF[0]);
	442	return TRUE;
	443	case 0xe3:
	444	if (EP0BUF[0] == 1)
	445	start_sampling();
	446	return TRUE;
	447	case 0xe4:
	448	set_numchannels(EP0BUF[0]);
	449	return TRUE;
75ad0fa5 BL	450	case 0xe5:
	451	set_coupling(EP0BUF[0]);
	452	return TRUE;
a425fae9 BL	453	case 0xe6:
	454	set_calibration_pulse(EP0BUF[0]);
	455	return TRUE;
ce1d0a86 BL	456	}
	457
	458	return FALSE; /* Not handled by handlers. */
	459	}
	460
	461	static void init(void)
	462	{
	463	EP4CFG = 0;
	464	EP8CFG = 0;
	465
be6d306d UH	466	SET_ANALOG_MODE();
be6d306d UH	467
ce1d0a86	468	/* In idle mode tristate all outputs. */
24373950 UH	469	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	470	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	471	GPIFWFSELECT = 0x00;
	472	GPIFREADYSTAT = 0x00;
	473
	474	stop_sampling();
	475
	476	set_voltage(0, 1);
	477	set_voltage(1, 1);
	478	set_samplerate(1);
	479	set_numchannels(2);
	480	select_interface(0);
	481	}
	482
	483	static void main(void)
	484	{
	485	/* Save energy. */
	486	SETCPUFREQ(CLK_12M);
	487
	488	init();
	489
	490	/* Set up interrupts. */
	491	USE_USB_INTS();
	492
	493	ENABLE_SUDAV();
	494	ENABLE_USBRESET();
	495	ENABLE_HISPEED();
	496	ENABLE_SUSPEND();
	497	ENABLE_RESUME();
	498
	499	/* Global (8051) interrupt enable. */
	500	EA = 1;
	501
	502	/* Init timer2. */
	503	RCAP2L = -1000 & 0xff;
386296a7	504	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	505	T2CON = 0;
	506	ET2 = 1;
	507	TR2 = 1;
	508
	509	RENUMERATE_UNCOND();
	510
	511	PORTCCFG = 0;
	512	PORTACFG = 0;
	513	PORTECFG = 0;
	514	OEE = 0xFF;
	515	OEC = 0xff;
	516	OEA = 0x80;
	517
be6d306d	518	SET_ANALOG_MODE();
ce1d0a86 BL	519
	520	while (TRUE) {
	521	if (dosud) {
	522	dosud = FALSE;
	523	handle_setupdata();
	524	}
	525
	526	if (dosuspend) {
	527	dosuspend = FALSE;
	528	do {
	529	/* Make sure ext wakeups are cleared. */
3968bbfb	530	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	531	SUSPEND = 1;
	532	PCON \|= 1;
	533	__asm
	534	nop
	535	nop
	536	nop
	537	nop
	538	nop
	539	nop
	540	nop
	541	__endasm;
	542	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	543
	544	/* Resume (TRM 6.4). */
	545	if (REMOTE_WAKEUP()) {
	546	delay(5);
	547	USBCS \|= bmSIGRESUME;
	548	delay(15);
	549	USBCS &= ~bmSIGRESUME;
	550	}
	551	}
	552	}
	553	}