Relevant comments from the linked thread in case the link gets broken:

In my case they are using hardware SPI in 16-bit mode in the microcontroller. The 93C86 memory expects a READ instruction which is 13 bits long. (SB (start bit)= 1, OPCODE = 10, ADDR = A9-A0). To align to 16 bits, the first 3 bits on MOSI are "0". Quote from datasheets: "If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition)." So the 93C86 recognizes the command only from the first bit in the "1" state. The protocol decoder in PulseView does not know this condition described in the documentation, therefore it cannot correctly recognize the communication. In attachment: Req. CLK Cycles 29 means 13 cycles per instruction + 16 cycles per data read.