Created attachment 758 [details] example vcd file If I try to import a VCD file that has strings into sigrok-cli or pulseview, I get an early termination or crash respectively. These strings are the result of a statemachine in a logic simulation. I would expect sigrok to ignore these if it cannot use them rather than crash. I have attached an example file. For example, I am running the following command: sigrok-cli -l 4 -O ascii -o output.txt -i uart.vcd --input-format vcd --protocol-decoder-samplenum -P uart:tx=bench.top.uart.tx_out:baudrate=2500000 and stdout is: sr: [00:00.000000] log: libsigrok loglevel set to 4. sr: [00:00.001296] backend: libsigrok 0.6.0-git-e1a712c/4:0:0. sr: [00:00.001482] backend: Libs: glib 2.48.2 (rt: 2.64.6/6406:6), zlib 1.2.8, libzip 1.0.1, minilzo 2.10, libserialport 0.1.1/1:0:1 (rt: 0.1.1/1:0:1), libusb-1.0 1.0.23.11397 API 0x01000104, hidapi 0.8.0-rc1, bluez 5.37, libftdi 1.2. sr: [00:00.001510] backend: Host: x86_64-pc-linux-gnu, little-endian. sr: [00:00.001515] backend: SCPI backends: TCP, RPC, serial, USBTMC. sr: [00:00.001516] backend: Firmware search paths: sr: [00:00.001575] backend: - /home/jeremy/.local/share/sigrok-firmware sr: [00:00.001601] backend: - /home/jenkins_slave/sr/share/sigrok-firmware sr: [00:00.001604] backend: - /tmp/.mount_sigrokXta9NL/usr/share/sigrok-firmware sr: [00:00.001605] backend: - /usr/share/xubuntu/sigrok-firmware sr: [00:00.001607] backend: - /usr/share/xfce4/sigrok-firmware sr: [00:00.001609] backend: - /usr/local/share/sigrok-firmware sr: [00:00.001610] backend: - /usr/share/sigrok-firmware sr: [00:00.001612] backend: - /var/lib/snapd/desktop/sigrok-firmware sr: [00:00.001614] backend: - /usr/share/sigrok-firmware srd: libsigrokdecode loglevel set to 4. srd: libsigrokdecode 0.6.0-git-8c44776/4:0:0 (rt: 0.6.0-git-8c44776/4:0:0). srd: Libs: glib 2.48.2 (rt: 2.64.6/6406:6), Python 3.5.2 / 0x30502f0 (API 1013, ABI 3). srd: Host: x86_64-pc-linux-gnu, little-endian. srd: Initializing libsigrokdecode. srd: Adding '/tmp/.mount_sigrokXta9NL/usr/share/libsigrokdecode/decoders' to module path. srd: Adding '/home/jenkins_slave/sr/share/libsigrokdecode/decoders' to module path. srd: Protocol decoder search paths: - /home/jenkins_slave/sr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokXta9NL/usr/share/libsigrokdecode/decoders srd: Python system search paths: - /home/jenkins_slave/sr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokXta9NL/usr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokXta9NL/usr/share/pyshared - /home/jeremy/Downloads - /tmp/.mount_sigrokXta9NL/usr/lib/python35.zip - /tmp/.mount_sigrokXta9NL/usr/lib/python3.5 - /tmp/.mount_sigrokXta9NL/usr/lib/python3.5/plat-x86_64-linux-gnu - /tmp/.mount_sigrokXta9NL/usr/lib/python3.5/lib-dynload srd: Creating session 1. srd: Creating new uart instance uart-1. srd: Registering new callback for output type OUTPUT_ANN. sr: [00:00.160994] input/vcd: Section 'comment', contents 'Generated by Amaranth'. sr: [00:00.161024] input/vcd: Section 'date', contents '2022-01-03 12:25:26.301455'. sr: [00:00.161026] input/vcd: Section 'timescale', contents '1 ps'. sr: [00:00.161031] input/vcd: Samplerate: 1000000000000 sr: [00:00.161033] input/vcd: Section 'scope', contents 'module bench'. sr: [00:00.161040] input/vcd: $scope, prefix now: "bench." sr: [00:00.161064] input/vcd: Section 'scope', contents 'module top'. sr: [00:00.161068] input/vcd: $scope, prefix now: "bench.top." sr: [00:00.161071] input/vcd: Section 'scope', contents 'module uart'. sr: [00:00.161074] input/vcd: $scope, prefix now: "bench.top.uart." sr: [00:00.161077] input/vcd: Section 'var', contents 'wire 1 ! clk'. sr: [00:00.161082] input/vcd: Section 'var', contents 'wire 1 " rst'. sr: [00:00.161088] input/vcd: Section 'var', contents 'wire 1 # tx_clkout'. sr: [00:00.161091] input/vcd: Section 'var', contents 'wire 1 $ output'. sr: [00:00.161096] input/vcd: Section 'var', contents 'wire 1 % tx_out'. sr: [00:00.161101] input/vcd: Section 'var', contents 'wire 4 & tx_data_count'. sr: [00:00.161104] input/vcd: Section 'var', contents 'wire 1 ' busy'. sr: [00:00.161106] input/vcd: Section 'var', contents 'wire 1 ( clear'. sr: [00:00.161109] input/vcd: Section 'var', contents 'string 1 ) fsm_state'. sr: [00:00.161112] input/vcd: Unsupported signal type: 'string' sr: [00:00.161114] input/vcd: Section 'var', contents 'wire 8 * tx_data_shadow'. sr: [00:00.161116] input/vcd: Section 'var', contents 'wire 1 + write_enable'. sr: [00:00.161119] input/vcd: Section 'var', contents 'wire 8 , data_in'. sr: [00:00.161161] input/vcd: Section 'scope', contents 'module clkdiv'. sr: [00:00.161165] input/vcd: $scope, prefix now: "bench.top.uart.clkdiv." sr: [00:00.161167] input/vcd: Section 'var', contents 'wire 1 ! clk'. sr: [00:00.161169] input/vcd: Section 'var', contents 'wire 1 " rst'. sr: [00:00.161172] input/vcd: Section 'var', contents 'wire 1 $ output'. sr: [00:00.161174] input/vcd: Section 'var', contents 'wire 1 ( clear'. sr: [00:00.161177] input/vcd: Section 'var', contents 'wire 3 - counter'. sr: [00:00.161180] input/vcd: Section 'upscope', contents ''. sr: [00:00.161186] input/vcd: $upscope, prefix now: "bench.top.uart." sr: [00:00.161189] input/vcd: Section 'upscope', contents ''. sr: [00:00.161190] input/vcd: $upscope, prefix now: "bench.top." sr: [00:00.161192] input/vcd: Section 'upscope', contents ''. sr: [00:00.161194] input/vcd: $upscope, prefix now: "bench." sr: [00:00.161196] input/vcd: Section 'upscope', contents ''. sr: [00:00.161198] input/vcd: $upscope, prefix now: "" sr: [00:00.161200] input/vcd: Section 'enddefinitions', contents ''. sr: [00:00.161204] input/vcd: sigrok channel idx 0, name bench.top.uart.clk, type L, en 1. sr: [00:00.161207] input/vcd: sigrok channel idx 1, name bench.top.uart.rst, type L, en 1. sr: [00:00.161210] input/vcd: sigrok channel idx 2, name bench.top.uart.tx_clkout, type L, en 1. sr: [00:00.161212] input/vcd: sigrok channel idx 3, name bench.top.uart.output, type L, en 1. sr: [00:00.161214] input/vcd: sigrok channel idx 4, name bench.top.uart.tx_out, type L, en 1. sr: [00:00.161216] input/vcd: sigrok channel idx 5, name bench.top.uart.tx_data_count.0, type L, en 1. sr: [00:00.161219] input/vcd: sigrok channel idx 6, name bench.top.uart.tx_data_count.1, type L, en 1. sr: [00:00.161221] input/vcd: sigrok channel idx 7, name bench.top.uart.tx_data_count.2, type L, en 1. sr: [00:00.161241] input/vcd: sigrok channel idx 8, name bench.top.uart.tx_data_count.3, type L, en 1. sr: [00:00.161246] input/vcd: sigrok channel idx 9, name bench.top.uart.busy, type L, en 1. sr: [00:00.161248] input/vcd: sigrok channel idx 10, name bench.top.uart.clear, type L, en 1. sr: [00:00.161251] input/vcd: sigrok channel idx 11, name bench.top.uart.tx_data_shadow.0, type L, en 1. sr: [00:00.161253] input/vcd: sigrok channel idx 12, name bench.top.uart.tx_data_shadow.1, type L, en 1. sr: [00:00.161255] input/vcd: sigrok channel idx 13, name bench.top.uart.tx_data_shadow.2, type L, en 1. sr: [00:00.161257] input/vcd: sigrok channel idx 14, name bench.top.uart.tx_data_shadow.3, type L, en 1. sr: [00:00.161260] input/vcd: sigrok channel idx 15, name bench.top.uart.tx_data_shadow.4, type L, en 1. sr: [00:00.161263] input/vcd: sigrok channel idx 16, name bench.top.uart.tx_data_shadow.5, type L, en 1. sr: [00:00.161266] input/vcd: sigrok channel idx 17, name bench.top.uart.tx_data_shadow.6, type L, en 1. sr: [00:00.161271] input/vcd: sigrok channel idx 18, name bench.top.uart.tx_data_shadow.7, type L, en 1. sr: [00:00.161274] input/vcd: sigrok channel idx 19, name bench.top.uart.write_enable, type L, en 1. sr: [00:00.161278] input/vcd: sigrok channel idx 20, name bench.top.uart.data_in.0, type L, en 1. sr: [00:00.161315] input/vcd: sigrok channel idx 21, name bench.top.uart.data_in.1, type L, en 1. sr: [00:00.161323] input/vcd: sigrok channel idx 22, name bench.top.uart.data_in.2, type L, en 1. sr: [00:00.161326] input/vcd: sigrok channel idx 23, name bench.top.uart.data_in.3, type L, en 1. sr: [00:00.161329] input/vcd: sigrok channel idx 24, name bench.top.uart.data_in.4, type L, en 1. sr: [00:00.161333] input/vcd: sigrok channel idx 25, name bench.top.uart.data_in.5, type L, en 1. sr: [00:00.161336] input/vcd: sigrok channel idx 26, name bench.top.uart.data_in.6, type L, en 1. sr: [00:00.161340] input/vcd: sigrok channel idx 27, name bench.top.uart.data_in.7, type L, en 1. sr: [00:00.161344] input/vcd: sigrok channel idx 28, name bench.top.uart.clkdiv.clk, type L, en 1. sr: [00:00.161346] input/vcd: sigrok channel idx 29, name bench.top.uart.clkdiv.rst, type L, en 1. sr: [00:00.161348] input/vcd: sigrok channel idx 30, name bench.top.uart.clkdiv.output, type L, en 1. sr: [00:00.161350] input/vcd: sigrok channel idx 31, name bench.top.uart.clkdiv.clear, type L, en 1. sr: [00:00.161374] input/vcd: sigrok channel idx 32, name bench.top.uart.clkdiv.counter.0, type L, en 1. sr: [00:00.161376] input/vcd: sigrok channel idx 33, name bench.top.uart.clkdiv.counter.1, type L, en 1. sr: [00:00.161379] input/vcd: sigrok channel idx 34, name bench.top.uart.clkdiv.counter.2, type L, en 1. srd: Setting channels for instance uart-1 with list of 1 channels. srd: Setting channel mapping: tx (PD ch idx 1) = input data ch idx 4. srd: Final channel map: srd: - PD ch idx 0 (rx) = input data ch idx -1 (optional) srd: - PD ch idx 1 (tx) = input data ch idx 4 (optional) sr: [00:00.161440] session: bus: Received SR_DF_HEADER packet. cli: Received SR_DF_HEADER. srd: Calling start() of all instances in session 1. srd: Calling start() of instance uart-1. srd: Instance uart-1 creating new output type OUTPUT_PYTHON as oid 0 (uart-1). srd: Instance uart-1 creating new output type OUTPUT_BINARY as oid 1 (uart-1). srd: Instance uart-1 creating new output type OUTPUT_ANN as oid 2 (uart-1). sr: [00:00.161619] session: bus: Received SR_DF_META packet. cli: Received SR_DF_META. cli: Got samplerate 1000000000000 Hz. srd: Setting session 1 samplerate to 1000000000000. sr: [00:00.161664] input/vcd: Seeding skip from first timestamp sr: [00:00.161668] input/vcd: $dumpvars section, will parse content sr: [00:00.161673] input/vcd: Unknown token 'sIDLE/0'. sr: [00:00.161681] session: bus: Received SR_DF_LOGIC packet (5 bytes, unitsize = 5). cli: Received SR_DF_LOGIC (5 bytes, unitsize = 5). srd: Decoding: abs start sample 0, abs end sample 1 (1 samples, 5 bytes, unitsize = 5), instance uart-1. srd: No worker thread for this decoder stack exists yet, creating one: uart-1. srd: uart-1: Starting thread routine for decoder. srd: uart-1: Calling decode(). srd: Done, handled all samples (abs cur 1 / abs end 1). sr: [00:00.161942] session: bus: Received SR_DF_END packet. cli: Received SR_DF_END. srd: End of sample data: instance uart-1. srd: uart-1: Decoder_wait: Raising EOF from wait(). srd: uart-1: decode() terminated. srd: uart-1: ignoring EOFError during decode() execution. srd: uart-1: decode() terminated (req 1). srd: uart-1: Thread done (with res). sr: [00:00.162025] input: Found 8306 unprocessed bytes at free time. srd: Exiting libsigrokdecode. srd: Freeing instance uart-1. srd: uart-1: Joining decoder thread. srd: uart-1: Raising want_term, sending got_new. srd: uart-1: Running join(). srd: uart-1: Call to join() done. srd: uart-1: Resetting decoder state. srd: uart-1: Releasing initial pin state. srd: Destroyed session 1. sr: [00:00.165065] hwdriver: Cleaning up all drivers. However, if I use GTKWave to extract just the signal of interest into a separate VCD file, it works fine: sr: [00:00.000000] log: libsigrok loglevel set to 4. sr: [00:00.001340] backend: libsigrok 0.6.0-git-e1a712c/4:0:0. sr: [00:00.001508] backend: Libs: glib 2.48.2 (rt: 2.64.6/6406:6), zlib 1.2.8, libzip 1.0.1, minilzo 2.10, libserialport 0.1.1/1:0:1 (rt: 0.1.1/1:0:1), libusb-1.0 1.0.23.11397 API 0x01000104, hidapi 0.8.0-rc1, bluez 5.37, libftdi 1.2. sr: [00:00.001535] backend: Host: x86_64-pc-linux-gnu, little-endian. sr: [00:00.001538] backend: SCPI backends: TCP, RPC, serial, USBTMC. sr: [00:00.001540] backend: Firmware search paths: sr: [00:00.001599] backend: - /home/jeremy/.local/share/sigrok-firmware sr: [00:00.001620] backend: - /home/jenkins_slave/sr/share/sigrok-firmware sr: [00:00.001622] backend: - /tmp/.mount_sigrokFXJ0J8/usr/share/sigrok-firmware sr: [00:00.001624] backend: - /usr/share/xubuntu/sigrok-firmware sr: [00:00.001626] backend: - /usr/share/xfce4/sigrok-firmware sr: [00:00.001627] backend: - /usr/local/share/sigrok-firmware sr: [00:00.001629] backend: - /usr/share/sigrok-firmware sr: [00:00.001630] backend: - /var/lib/snapd/desktop/sigrok-firmware sr: [00:00.001632] backend: - /usr/share/sigrok-firmware srd: libsigrokdecode loglevel set to 4. srd: libsigrokdecode 0.6.0-git-8c44776/4:0:0 (rt: 0.6.0-git-8c44776/4:0:0). srd: Libs: glib 2.48.2 (rt: 2.64.6/6406:6), Python 3.5.2 / 0x30502f0 (API 1013, ABI 3). srd: Host: x86_64-pc-linux-gnu, little-endian. srd: Initializing libsigrokdecode. srd: Adding '/tmp/.mount_sigrokFXJ0J8/usr/share/libsigrokdecode/decoders' to module path. srd: Adding '/home/jenkins_slave/sr/share/libsigrokdecode/decoders' to module path. srd: Protocol decoder search paths: - /home/jenkins_slave/sr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokFXJ0J8/usr/share/libsigrokdecode/decoders srd: Python system search paths: - /home/jenkins_slave/sr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokFXJ0J8/usr/share/libsigrokdecode/decoders - /tmp/.mount_sigrokFXJ0J8/usr/share/pyshared - /home/jeremy/Downloads - /tmp/.mount_sigrokFXJ0J8/usr/lib/python35.zip - /tmp/.mount_sigrokFXJ0J8/usr/lib/python3.5 - /tmp/.mount_sigrokFXJ0J8/usr/lib/python3.5/plat-x86_64-linux-gnu - /tmp/.mount_sigrokFXJ0J8/usr/lib/python3.5/lib-dynload srd: Creating session 1. srd: Creating new uart instance uart-1. srd: Registering new callback for output type OUTPUT_ANN. sr: [00:00.162026] input/vcd: Section 'date', contents 'Sun Jan 2 18:27:12 2022'. sr: [00:00.162055] input/vcd: Section 'version', contents 'GTKWave Analyzer v3.3.103 (w)1999-2019 BSI'. sr: [00:00.162059] input/vcd: Section 'timescale', contents '1ps'. sr: [00:00.162063] input/vcd: Samplerate: 1000000000000 sr: [00:00.162065] input/vcd: Section 'scope', contents 'module bench'. sr: [00:00.162072] input/vcd: $scope, prefix now: "bench." sr: [00:00.162091] input/vcd: Section 'scope', contents 'module top'. sr: [00:00.162095] input/vcd: $scope, prefix now: "bench.top." sr: [00:00.162097] input/vcd: Section 'scope', contents 'module uart'. sr: [00:00.162100] input/vcd: $scope, prefix now: "bench.top.uart." sr: [00:00.162102] input/vcd: Section 'var', contents 'wire 1 " tx_out'. sr: [00:00.162111] input/vcd: Section 'upscope', contents ''. sr: [00:00.162115] input/vcd: $upscope, prefix now: "bench.top." sr: [00:00.162118] input/vcd: Section 'upscope', contents ''. sr: [00:00.162121] input/vcd: $upscope, prefix now: "bench." sr: [00:00.162123] input/vcd: Section 'upscope', contents ''. sr: [00:00.162147] input/vcd: $upscope, prefix now: "" sr: [00:00.162150] input/vcd: Section 'enddefinitions', contents ''. sr: [00:00.162152] input/vcd: sigrok channel idx 0, name bench.top.uart.tx_out, type L, en 1. srd: Setting channels for instance uart-1 with list of 1 channels. srd: Setting channel mapping: tx (PD ch idx 1) = input data ch idx 0. srd: Final channel map: srd: - PD ch idx 0 (rx) = input data ch idx -1 (optional) srd: - PD ch idx 1 (tx) = input data ch idx 0 (optional) sr: [00:00.162189] session: bus: Received SR_DF_HEADER packet. cli: Received SR_DF_HEADER. srd: Calling start() of all instances in session 1. srd: Calling start() of instance uart-1. srd: Instance uart-1 creating new output type OUTPUT_PYTHON as oid 0 (uart-1). srd: Instance uart-1 creating new output type OUTPUT_BINARY as oid 1 (uart-1). srd: Instance uart-1 creating new output type OUTPUT_ANN as oid 2 (uart-1). sr: [00:00.162295] session: bus: Received SR_DF_META packet. cli: Received SR_DF_META. cli: Got samplerate 1000000000000 Hz. srd: Setting session 1 samplerate to 1000000000000. sr: [00:00.162318] input/vcd: Seeding skip from first timestamp sr: [00:00.162340] input/vcd: $dumpvars section, will parse content sr: [00:00.162342] input/vcd: done ignoring $end keyword sr: [00:00.172824] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 0, abs end sample 4194304 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: No worker thread for this decoder stack exists yet, creating one: uart-1. srd: uart-1: Starting thread routine for decoder. srd: uart-1: Calling decode(). 208330-608330 uart-1: tx-start: "Start bit" "Start" "S" 608330-1008330 uart-1: tx-data-bit: "0" 1008330-1408330 uart-1: tx-data-bit: "1" 1408330-1808330 uart-1: tx-data-bit: "0" 1808330-2208330 uart-1: tx-data-bit: "1" 2208330-2608330 uart-1: tx-data-bit: "0" 2608330-3008330 uart-1: tx-data-bit: "1" 3008330-3408330 uart-1: tx-data-bit: "0" 3408330-3808330 uart-1: tx-data-bit: "1" 608330-3808330 uart-1: tx-data: "AA" 3808330-4208330 uart-1: tx-stop: "Stop bit" "Stop" "T" srd: Done, handled all samples (abs cur 4194304 / abs end 4194304). sr: [00:00.232641] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 4194304, abs end sample 8388608 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 8388608 / abs end 8388608). sr: [00:00.301782] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 8388608, abs end sample 12582912 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 12582912 / abs end 12582912). sr: [00:00.367041] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 12582912, abs end sample 16777216 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 16777216 / abs end 16777216). sr: [00:00.432729] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 16777216, abs end sample 20971520 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 20971520 / abs end 20971520). sr: [00:00.503038] session: bus: Received SR_DF_LOGIC packet (4194304 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (4194304 bytes, unitsize = 1). srd: Decoding: abs start sample 20971520, abs end sample 25165824 (4194304 samples, 4194304 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 25165824 / abs end 25165824). sr: [00:00.559805] session: bus: Received SR_DF_LOGIC packet (83772 bytes, unitsize = 1). cli: Received SR_DF_LOGIC (83772 bytes, unitsize = 1). srd: Decoding: abs start sample 25165824, abs end sample 25249596 (83772 samples, 83772 bytes, unitsize = 1), instance uart-1. srd: Done, handled all samples (abs cur 25249596 / abs end 25249596). sr: [00:00.561233] input/vcd: TS post stats: oversample unscaled 208330, scaled 208330 sr: [00:00.561278] input/vcd: Suspiciously low overall change rate (total min TS delta 208330). sr: [00:00.561281] input/vcd: Suggest to downsample, value like 100000. sr: [00:00.561306] session: bus: Received SR_DF_END packet. cli: Received SR_DF_END. srd: End of sample data: instance uart-1. srd: uart-1: Decoder_wait: Raising EOF from wait(). srd: uart-1: decode() terminated. srd: uart-1: ignoring EOFError during decode() execution. srd: uart-1: decode() terminated (req 1). srd: uart-1: Thread done (with res). srd: Exiting libsigrokdecode. srd: Freeing instance uart-1. srd: uart-1: Joining decoder thread. srd: uart-1: Raising want_term, sending got_new. srd: uart-1: Running join(). srd: uart-1: Call to join() done. srd: uart-1: Resetting decoder state. srd: uart-1: Releasing initial pin state. srd: Destroyed session 1. sr: [00:00.564650] hwdriver: Cleaning up all drivers.
There are several issues at play, let's keep the concepts clear. The import does not crash, it terminates when unsupported data is seen. The sigrok project has no concept of string data, and the VCD file format (as far as I'm aware) doesn't either. Have yet to see a spec what "a string" is supposed to look like in a VCD file. Mind you: a spec, not an arbitrary implementation like gtkwave or migen, which may or may not be a local extension of these implementations, and not an official VCD feature. The termination of the import upon sight of unsupported input data is to be expected. If you want to see support for strings in VCD, provide a reliable source of information so that proper support can get implemented. This was discussed in IRC after I became aware of the libsigrok pull request on github (the implementation of which is not suitable for mainline sigrok, a proper spec is required to resolve that). The diagnostics message about the unsupported signal data type unfortunately has too low a severity. Current mainline uses INFO which is not perceivable by users by default. I'll fix that and make it ERROR as it should be, the condition is fatal after all. Compare log level 3 output which should not drown you in debug level details. When the pulseview application keeps attempting to read the data part (the value changes) in the file after parsing the header failed, then that's an issue which should have its own report. May affect other file formats, too, and is not strictly related to VCD and strings.
Have created bug 1758 for the pulseview application part where failed headers should terminate the import, and not advance to the data part of the file.
Thank you Gerhard, I did not realise that this was a non-standard extension of the VCD format. And yes, the crash I was referring to was not in libsigrok, but rather pulseview (it segfaulted). It seems this issue has also come up in GHDL: https://github.com/ghdl/ghdl/issues/647 I am happy for you to close this if you wish.
Would you be willing to accept a patch which just ignores strings? It could be off by default.
Regarding "just ignore strings": Depends on how it's done. The simple brute force approach originally taken in https://github.com/sigrokproject/libsigrok/pull/157 is most certainly not acceptable (silently(!) ignores input data based on too weak a condition). Emitting diagnostics for each occurance of something unknown in the data section would be pointless, too (too noisy and users no longer see messages which genuinely require attention). I'd like to have something that is both useful and reliable. Granted it's more work, but this effort is spent for both the users and the developers who are supposed to maintain this code base. So it's well spent. And it's important to keep in mind that the issue at hand really is not as trivial as it appears at first sight. What the sigrok project needs is feedback on what exactly "a string" is supposed to be, so that valid data can get accepted (skipped when seen) _and_ invalid data can get rejected. I'd even accept absence of "an official standard", but having a plausible concept that reliably works is essential. Would hate an ad hoc approach that needs tweaks every other week in back and forth ways just to process the data of today as example files are seen, and still lack an idea what valid syntax would be. Can I get feedback on https://repo.or.cz/libsigrok/gsi.git/shortlog/refs/heads/wip/vcd-string-type-v1 and especially on https://repo.or.cz/libsigrok/gsi.git/commitdiff/9a2955ec85e6f202fe71dbde19191f7eb53fcacc please? The HEAD commit of that branch prepares the acceptance of more types which don't map to sigrok internals yet are considered plausible upon import.
I have asked whitequark (who maintains amaranth [previously nmigen]) to comment on this: https://github.com/amaranth-lang/amaranth/issues/675 Hopefully they have a chance to look at this and share some feedback. As far as the git commits you have linked, they seem good to me. Overall, I think safely ignoring the strings is perfectly fine as they don’t really fit into the sigrok usage model. As far as the assumptions made: - ASCII only: sounds reasonable - no white space: sounds reasonable - escape sequences: personally, I think this is not necessary but I can see the rationale for including them (ie “do it once, do it right”)
Also a useful comment here: https://github.com/westerndigitalcorporation/pyvcd/issues/17
whitequark also sent this in response (see https://github.com/amaranth-lang/amaranth/issues/675#issuecomment-1006486925 ) --- https://repo.or.cz/libsigrok/gsi.git/commitdiff/9a2955ec85e6f202fe71dbde19191f7eb53fcacc This commit looks fine. Regarding this: System Verilog is said to support strings but would not discuss how to represent them in VCD files. The IEEE standard is said to not be open. Hmm ... Indeed, there's nothing in IEEE 1800-2017 about dumping strings to VCD files. ---
Commit c1310f7deba7 implements support for graceful skipping of strings in VCD input files. Feel free to throw as many files as you can at this code, to see whether the validity check needs more adjustment.
Thank you! Will reinstall the nightly in a few days and give it a go.