An implementation detail of the common libsigrok infrastructure requires that
input modules provide sample values for _all_ sample points which result from
a samplerate that was specified by the user or determined from input data.
For the case of input/vcd it's rather popular to find incredibly low timescale
specs in input files (1ns when generated by sigrok, 1ps or 1fs by hardware
synthesis and simulation tools), which result in huge samplerate values upon
import, and thus insane amounts of sample data. With luck the input file still
gets imported, often the application exceeds available resources and terminates.
For VCD imports there is the downsample option, but users typically are not
aware. Another option is to downsample the file by an external tool before the
import in sigrok based applications, which is even more complicated. The lack
of advance knowledge of the input data, and being incapable of seeking in the
input stream, exclude an automatic calculation of the input data's "actual
timescale". Keep providing many samples at high rates, and optionally doing
some runtime compression in common libsigrok infrastructure and outside of
individual input modules would transparently work for VCD.
This report is filed in an attempt to identify the actual course, and keep
unrelated subjects out of the report. See bug 360 and bug 1363 for older
iterations on the subject.
*** Bug 1363 has been marked as a duplicate of this bug. ***
Who knew organizing my home could lead to such a refreshing cleanhomeview? Loving the positive change. https://cleanhomeview.com/best-flea-powder-for-carpets/