Created attachment 496 [details]
UART PD output, overlapping frames

The UART protocol decoder is usable for correct input streams.  A minor nit 
that kept bothering me is the inaccurate ss/es calculation which results in 
overlapping annotations and slightly ambiguous decoder output (there are 
periods of time which claim that two bits of a UART frame would be active 
at the same time).  This is assumed to be due to floating point rounding of 
fractional sample counts, and partly due to redundant (re-)calculations of 
sample positions.

Another issue is that robustness of the decoder for unexpected or incorrect 
input streams could get improved:
- The START of new UART frames "gets detected" in the middle of a previous 
  frame's STOP bit time.
- Subsequent START bits get detected and overlap when input data jitters or 
  the input stream's bit rate does not match the current setting.
- One might consider adding an "oversampling" option, which on one hand could 
  result in different output than the current implementation for unclean input, 
  but also could result in more reliable data extraction for the same kind of 
  unclean input (users should decide which they prefer, hiding issues or 
  highlighting them).
- Code paths in the current implementation can skip data extraction and their 
  presentation when error paths abort inspection before that step.  Users may 
  prefer to always see extracted data, and have it amended with error markers 
  where appropriate.
- Parity error annotations carry fixed and potentially wrong data values.