Attachment 421 Details for Bug 1194 – VCD file itself causing the issue

VCD file itself causing the issue

dump.vcd (text/plain), 1.09 KB, created by hak8or on 2018-05-11 12:51:11 CEST

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Creator: hak8or

Created: 2018-05-11 12:51:11 CEST

Size: 1.09 KB

patch

obsolete

>$date
>	Thu May 10 22:31:28 2018
>$end
>$version
>	Icarus Verilog
>$end
>$timescale
>	1s
>$end
>$scope module UART_TB $end
>$var wire 1 ! PIN $end
>$var wire 1 " DONE $end
>$var reg 1 # CLK $end
>$var reg 8 $ DATA [7:0] $end
>$var reg 1 % WRITE $end
>$scope module uart $end
>$var wire 1 # clk $end
>$var wire 8 & data [7:0] $end
>$var wire 1 % write $end
>$var reg 8 ' Data_Buffer [7:0] $end
>$var reg 8 ( SM [7:0] $end
>$var reg 1 " done $end
>$var reg 1 ! pin $end
>$upscope $end
>$upscope $end
>$enddefinitions $end
>#0
>$dumpvars
>b0 (
>b0 '
>b0 &
>0%
>b0 $
>0#
>x"
>x!
>$end
>#1
>1"
>1!
>1#
>#2
>0#
>b1100101 $
>b1100101 &
>#3
>1#
>#4
>0#
>1%
>#5
>b1 (
>b1100101 '
>1#
>#6
>0#
>#7
>b10 (
>0!
>1#
>#8
>0#
>b0 $
>b0 &
>#9
>b11 (
>0"
>b110010 '
>1!
>1#
>#10
>0#
>#11
>b100 (
>b11001 '
>0!
>1#
>#12
>0#
>0%
>#13
>b101 (
>b1100 '
>1!
>1#
>#14
>0#
>#15
>b110 (
>b110 '
>0!
>1#
>#16
>0#
>#17
>b111 (
>b11 '
>1#
>#18
>0#
>#19
>b1000 (
>b1 '
>1!
>1#
>#20
>0#
>#21
>b1001 (
>b0 '
>1#
>#22
>0#
>#23
>b1010 (
>0!
>1#
>#24
>0#
>#25
>1!
>b1011 (
>1#
>#26
>0#
>#27
>1"
>b0 (
>1!
>1#
>#28
>0#
>#29
>1#
>#30
>0#
>#31
>1#
>#32
>0#

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