Difference between revisions of "HT USBee-AxPro"

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=== Analog frontend ===
[http://sigrok.org/wiki/File:Ht-usbee-axpro_analog_schematics.svg Schematics]
Notes:
* Some devices have R2 = 66.5 Ohms instead of kiloohms, this basically limits the range to -3.3V — +3.3V
* TLC5510 is used with ~3.3V "reference" from LDO output which is both out of the allowed range and is a major source of inaccuracy
* Some devices (probably those that do not have U5 populated) produce bogus min and max spikes when measuring certain voltages, this can probably be remedied by adding small (on the order of 10s pF) capacitance to U5 Vcc and GND pins or to the ADC CLK line
* This board was apparently designed by people lacking EE knowledge, do not expect much from it


'''HT_V6.0''':
'''HT_V6.0''':

Revision as of 22:41, 16 July 2016

HT USBee-AxPro
Ht-usbee-axpro.png
Status supported
Source code fx2lafw
Channels 8 + 1
Samplerate 24MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage Digital: -1V — +6V
Analog: ±10V (±20V max)
Threshold voltage Fixed: VIH=1.6V, VIL=1.4V
Memory none
Compression none
Website aliexpress.com

The HT USBee-AxPro is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate, with 1 additional analog channel.

It is able to switch between USBee AX-Pro, Salea Logic and Altera USB blaster mode via a button. When pressing the button the USB VID/PID changes.

It is a clone of the CWAV USBee AX-Pro.

In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.

See HT USBee-AxPro/Info for some more details (such as lsusb -v output) on the device.

Hardware

HT2013 V5.00:

FX2LP pin mappings

# Pin Destination Remark
CTL2 ADC_CLK ADC clock
PD0..7 ADC_D1..8 ADC data output

Analog frontend

Schematics

Notes:

  • Some devices have R2 = 66.5 Ohms instead of kiloohms, this basically limits the range to -3.3V — +3.3V
  • TLC5510 is used with ~3.3V "reference" from LDO output which is both out of the allowed range and is a major source of inaccuracy
  • Some devices (probably those that do not have U5 populated) produce bogus min and max spikes when measuring certain voltages, this can probably be remedied by adding small (on the order of 10s pF) capacitance to U5 Vcc and GND pins or to the ADC CLK line
  • This board was apparently designed by people lacking EE knowledge, do not expect much from it

HT_V6.0:

  • ...

Pin mappings

The FX2 CTL2 and PD0..7 pins are mapped exactly like the HT2013 V5.00 version. The TLC5510I OE# pin is tied to GND.

Photos

HT2013 V5.00:

HT2013 V5.00 (no blue button PCB):

HT_V6.0:

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources