Difference between revisions of "HT USBee-AxPro"

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(HT_V6.0)
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'''HT2013 V5.00''':
'''HT2013 V5.00''':
<gallery>
<gallery>
File:Ht-usbee-axpro_package.jpg |<small>Device package</small>
File:Ht-usbee-axpro_package.jpg |<small>Device package</small>
Line 82: Line 83:


'''HT_V6.0''':
'''HT_V6.0''':
<gallery>
<gallery>
File:Ht usbee axpro package contents.jpg|<small>Package contents</small>
File:Ht usbee axpro device top.jpg|<small>Device, top</small>
File:Ht usbee axpro device bottom.jpg|<small>Device, bottom</small>
File:Ht usbee axpro connector.jpg|<small>Connector</small>
File:Ht usbee axpro usb.jpg|<small>USB</small>
File:Ht usbee axpro analog adapter top.jpg|<small>Analog adapter, top</small>
File:Ht usbee axpro analog adapter bottom.jpg|<small>Analog adapter, bottom</small>
File:Ht usbee axpro pcb top.jpg|<small>PCB, top</small>
File:Ht usbee axpro pcb bottom.jpg|<small>PCB, bottom</small>
File:Ht usbee axpro cypress fx2.jpg|<small>Cypress FX2</small>
File:Ht usbee axpro microchip 24lc02b.jpg|<small>Microchip 24LC02B</small>
File:Ht usbee axpro tlc5510i.jpg|<small>TI TLC5510I</small>
File:Ht usbee axpro intersil icl7660s.jpg|<small>Intersil ICL7660S</small>
File:Ht usbee axpro ams1117-3.3.jpg|<small>AMS1117-3.3</small>
File:Ht usbee axpro hra.jpg|<small>HRA</small>
File:Ht usbee axpro 24mhz crystal.jpg|<small>24MHz crystal</small>
</gallery>
</gallery>



Revision as of 16:34, 3 July 2016

HT USBee-AxPro
Ht-usbee-axpro.png
Status supported
Source code fx2lafw
Channels 8
Samplerate 24MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage Digital: -1V — +6V
Analog: ±10V (±20V max)
Threshold voltage Fixed: VIH=1.6V, VIL=1.4V
Memory none
Compression none

The HT USBee-AxPro is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate, with 1 additional analog channel.

It is able to switch between USBee AX-Pro, Salea Logic and Altera USB blaster mode via a button. When pressing the button the USB VID/PID changes.

It is a clone of the CWAV USBee AX-Pro.

In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.

Hardware

HT2013 V5.00:

FX2LP pin mappings

# Pin Destination Remark
CTL2 ADC_CLK ADC clock
PD0..7 ADC_D1..8 ADC data output


HT_V6.0:

  • ...

Pin mappings

The FX2 CTL2 and PD0..7 pins are mapped exactly like the HT2013 V5.00 version. The TLC5510I OE# pin is tied to GND.

Photos

HT2013 V5.00:

HT_V6.0:

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources