Difference between revisions of "Protocol decoder:Z80"
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(Create initial Z80 decoder page) |
Uwe Hermann (talk | contribs) m |
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| name = Z80 | | name = Z80 | ||
| description = Zilog Z80 microprocessor disassembly | | description = Zilog Z80 microprocessor disassembly | ||
| status = | | status = supported | ||
| license = | | license = GPLv3+ | ||
| source_code_dir = z80 | | source_code_dir = z80 | ||
| image = [[File:Z80 decoder example.png]] | | image = [[File:Z80 decoder example.png|250px]] | ||
| input = logic | | input = logic | ||
| output = z80 | | output = z80 | ||
| probes = D0–D7, /M1, /RD, /WR | | probes = D0–D7, /M1, /RD, /WR | ||
| optional_probes = /MREQ, /IORQ, A0–A15 | | optional_probes = /MREQ, /IORQ, A0–A15 | ||
| options = — | |||
}} | }} | ||
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== Resources == | == Resources == | ||
* [https://en.wikipedia.org/wiki/Zilog_Z80 Wikipedia: Zilog Z80] | |||
[[Category:Protocol decoder]] | [[Category:Protocol decoder]] | ||
Latest revision as of 23:14, 2 April 2015
 | |
| Name | Z80 |
|---|---|
| Description | Zilog Z80 microprocessor disassembly |
| Status | supported |
| License | GPLv3+ |
| Source code | decoders/z80 |
| Input | logic |
| Output | z80 |
| Probes | D0–D7, /M1, /RD, /WR |
| Optional probes | /MREQ, /IORQ, A0–A15 |
| Options | — |
The z80 protocol decoder disassembles the instruction stream of a Zilog Z80 microprocessor.
Hardware
KC 85/4
The z80/kc85 directory in sigrok-dumps contains a set of example bus captures of the Z80-based KC 85/4 computer.
The logic analyzer used was a Sysclk LWLA1034.
Protocol
The data bus lines plus the control signals /M1, /RD and /WR are sufficient to display full disassembly. Optionally, the address bus lines and the control signals /MREQ and /IORQ may also be provided.