Difference between revisions of "ChronoVu LA8"
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TODO | TODO | ||
=== Sampling === | |||
The device has an 8MB buffer (SDRAM) which is always filled completely with samples. Using the '''divcount''' divider value (valid range: 0x00 - 0xfe) samplerates between 100MHz and 392.15kHz can be selected. Depending on the samplerate different total sampling times (from 0.084s up to 21.391s) can be achieved. | |||
The formula for the sample period (not to be confused with the samplerate) is: | |||
sample period = (divcount + 1) * 10ns | |||
The following table shows a small part of the valid divcount values and resulting samplerates and sampling times. | |||
{| border="0" style="font-size: smaller" | |||
|- bgcolor="#6699ff" | |||
!Divider | |||
!Sample period | |||
!Samplerate | |||
!Sampling time | |||
|- bgcolor="#eeeeee" | |||
| 0x00 | |||
| 10ns | |||
| 100MHz | |||
| 0.084s | |||
|- bgcolor="#dddddd" | |||
| ... | |||
| ... | |||
| ... | |||
| ... | |||
|- bgcolor="#eeeeee" | |||
| 0xfe | |||
| 2550ns | |||
| 392.15kHz | |||
| 21.391s | |||
|} | |||
== Usage == | == Usage == | ||
Revision as of 13:32, 10 April 2011
The ChronoVu LA8 is a USB-based 8-channel logic analyzer with up to 100MHz sampling rate. It features a Xilinx CPLD for sampling, 8MB of built-in SDRAM to store the samples, and can trigger on low or high states of any combination of probes. After the 8MB sample buffer is full, the data is transferred to the host using an FTDI USB-to-serial chip.
See ChronoVu LA8/Info for more details (such as lsusb -vvv output) about the device.
Thanks
Many thanks to the vendor (ChronoVu) for freely providing information on the protocol used to communicate with the device. This helped us implement the sigrok hardware driver more quickly. We're happy to see more open-source friendly vendors support sigrok!
Hardware
- Xilinx XC2C256 CoolRunner-II CPLD
- Micron MT48LC4M16A2 SDRAM (8 MByte)
- FTDI FT245RL
- LXH244A (buffer)
- PT70151
Protocol
TODO
Sampling
The device has an 8MB buffer (SDRAM) which is always filled completely with samples. Using the divcount divider value (valid range: 0x00 - 0xfe) samplerates between 100MHz and 392.15kHz can be selected. Depending on the samplerate different total sampling times (from 0.084s up to 21.391s) can be achieved.
The formula for the sample period (not to be confused with the samplerate) is:
sample period = (divcount + 1) * 10ns
The following table shows a small part of the valid divcount values and resulting samplerates and sampling times.
| Divider | Sample period | Samplerate | Sampling time |
|---|---|---|---|
| 0x00 | 10ns | 100MHz | 0.084s |
| ... | ... | ... | ... |
| 0xfe | 2550ns | 392.15kHz | 21.391s |
Usage
$ sigrok-cli -d chronovu-la8 --samples 8388603 -f binary > samples.dat
The default samplerate is 100MHz (which results in a sampling time of 0.084s). To select another sampling rate use this syntax:
$ sigrok-cli -d chronovu-la8:samplerate=1mhz --samples 8388603 -f binary > samples.dat
TODO
- Implement input and output file format support for the ChronoVu LA8 software for interoperability.
- Implement proper trigger support.
- Implement --time and --samples correctly, currently you can only get exactly 8388603 (8MB) samples.
More photos
Device with probes
USB and LEDs
Probe connector
PCB, front
PCB, back
Xilinx CPLD
SDRAM chip
FTDI chip
See also [ this flickr set] for more PCB photos of the device.