uart: Add test-cases for rx_packet_delimiter/rx_packet_len et al.

[sigrok-test.git] / decoder / test / uart / uart_count_19200_5n1_dec.output

diff --git a/decoder/test/uart/uart_count_19200_5n1_dec.output b/decoder/test/uart/uart_count_19200_5n1_dec.output
index e94688107f252b9f55d5716810ead603f54f6337..e9d37c45441bc7a7cec0c0b01b70ff94d49fb756 100644 (file)
--- a/decoder/test/uart/uart_count_19200_5n1_dec.output
+++ b/decoder/test/uart/uart_count_19200_5n1_dec.output
@@ -125,6 +125,7 @@
 6807-6834 uart: tx-data-bits: "1"
 6833-6860 uart: tx-data-bits: "0"
 6729-6860 uart: tx-data: "14"
+143-6860 uart: tx-packet: "31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14"
 6859-6886 uart: tx-parity-ok: "Stop bit" "Stop" "T"
 7141-7168 uart: tx-start: "Start bit" "Start" "S"
 7167-7194 uart: tx-data-bits: "1"
@@ -253,6 +254,7 @@
 13821-13848 uart: tx-data-bits: "1"
 13847-13874 uart: tx-data-bits: "1"
 13743-13874 uart: tx-data: "30"
+7167-13874 uart: tx-packet: "15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30"
 13873-13900 uart: tx-parity-ok: "Stop bit" "Stop" "T"
 14153-14180 uart: tx-start: "Start bit" "Start" "S"
 14179-14206 uart: tx-data-bits: "1"
@@ -381,6 +383,7 @@
 20843-20870 uart: tx-data-bits: "1"
 20869-20896 uart: tx-data-bits: "0"
 20765-20896 uart: tx-data: "14"
+14179-20896 uart: tx-packet: "31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14"
 20895-20922 uart: tx-parity-ok: "Stop bit" "Stop" "T"
 21177-21204 uart: tx-start: "Start bit" "Start" "S"
 21203-21230 uart: tx-data-bits: "1"
@@ -509,6 +512,7 @@
 27857-27884 uart: tx-data-bits: "1"
 27883-27910 uart: tx-data-bits: "1"
 27779-27910 uart: tx-data: "30"
+21203-27910 uart: tx-packet: "15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30"
 27909-27936 uart: tx-parity-ok: "Stop bit" "Stop" "T"
 28189-28216 uart: tx-start: "Start bit" "Start" "S"
 28215-28242 uart: tx-data-bits: "1"