/*
- * This file is part of the fx2lafw project.
+ * This file is part of the sigrok-firmware-fx2lafw project.
*
* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>
-
#include <fx2lafw.h>
#include <gpif-acquisition.h>
-/* GPIF terminology: DP = decision point, NDP = non-decision-point */
-
-/*
- * GPIF waveforms.
- *
- * See section "10.3.4 State Instructions" in the TRM for details.
- */
-static const BYTE wavedata[128] = {
- /* Waveform 0: */
-
- /*
- * This is the basic algorithm implemented in our GPIF state machine:
- *
- * State 0: NDP: Sample the FIFO data bus.
- * State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
- * end the current waveform. Otherwise, go to state 0 again,
- * i.e., sample data until EP2 is full.
- * State 2: Unused.
- * State 3: Unused.
- * State 4: Unused.
- * State 5: Unused.
- * State 6: Unused.
- */
-
- /* S0-S6: LENGTH/BRANCH */
- /*
- * For NDPs (LENGTH): Number of IFCLK cycles to stay in this state.
- * For DPs (BRANCH): [7] ReExec, [5:3]: BRANCHON1, [2:0]: BRANCHON0.
- *
- * 0x01: Stay one IFCLK cycle in this state.
- * 0x38: No Re-execution, BRANCHON1 = state 7, BRANCHON0 = state 0.
- */
- // 0x01, 0x38, 0x01, 0x01, 0x01, 0x01, 0x01,
- // FIXME: For now just loop over the "sample data" state forever.
- 0x01, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,
- /* TRM says "reserved", but GPIF designer always puts a 0x07 here. */
- 0x07,
-
- /* S0-S6: OPCODE */
- /*
- * 0x02: NDP, sample the FIFO data bus.
- * 0x01: DP, don't sample the FIFO data bus.
- */
- 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* Reserved */
- 0x00,
+__bit gpif_acquiring;
- /* S0-S6: OUTPUT */
- /* Unused, we don't output anything, we only sample the pins. */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* Reserved */
- 0x00,
+static void gpif_reset_waveforms(void)
+{
+ int i;
- /* S0-S6: LOGIC FUNCTION (not used for NDPs) */
- /*
- * 0x36: LFUNC = "A AND B", A = FIFO flag, B = FIFO flag.
- * The FIFO flag (FF == full flag, in our case) is configured via
- * EP2GPIFFLGSEL.
- *
- * So: If the EP2 FIFO is full and the EP2 FIFO is full, go to
- * the state specified by BRANCHON1 (state 7), otherwise BRANCHON0
- * (state 0). See the LENGTH/BRANCH value above for details.
- */
- 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* TRM says "reserved", but GPIF designer always puts a 0x3f here. */
- 0x3f,
-
- /* TODO: Must unused waveforms be "valid"? */
-
- /* Waveform 1 (unused): */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* Waveform 2 (unused): */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* Waveform 3 (unused): */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
+ /* Reset WAVEDATA. */
+ AUTOPTRSETUP = 0x03;
+ AUTOPTRH1 = 0xe4;
+ AUTOPTRL1 = 0x00;
+ for (i = 0; i < 128; i++)
+ EXTAUTODAT1 = 0;
+}
static void gpif_setup_registers(void)
{
/* When GPIF is idle, tri-state the data bus. */
/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
- GPIFIDLECS = (1 << 0);
+ GPIFIDLECS = (0 << 0);
/* When GPIF is idle, set CTL0-CTL5 to 0. */
GPIFIDLECTL = 0;
/*
- * Map index 0 in wavedata[] to FIFORD. The rest is assigned too,
+ * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
* but not used by us.
*
* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
/* Contains RDY* pin values. Read-only according to TRM. */
GPIFREADYSTAT = 0;
-}
-
-static void gpif_write_waveforms(void)
-{
- int i;
- /*
- * Write the four waveforms into the respective WAVEDATA register
- * locations (0xe400 - 0xe47f) using the FX2's autopointer feature.
- */
- AUTOPTRSETUP = 0x07; /* Increment autopointers 1 & 2. */
- AUTOPTRH1 = MSB((WORD)wavedata); /* Source is the 'wavedata' array. */
- AUTOPTRL1 = LSB((WORD)wavedata);
- AUTOPTRH2 = 0xe4; /* Dest is WAVEDATA (0xe400). */
- AUTOPTRL2 = 0x00;
- for (i = 0; i < 128; i++)
- EXTAUTODAT2 = EXTAUTODAT1;
+ /* Make GPIF stop on transaction count not flag. */
+ EP2GPIFPFSTOP = (0 << 0);
}
static void gpif_init_addr_pins(void)
/* Setup the GPIF registers. */
gpif_setup_registers();
- /* Write the four GPIF waveforms into the WAVEDATA register. */
- gpif_write_waveforms();
+ /* Reset WAVEDATA. */
+ gpif_reset_waveforms();
/* Initialize GPIF address pins, output initial values. */
gpif_init_addr_pins();
/* Initialize flowstate registers (not used by us). */
gpif_init_flowstates();
+
+ /* Reset the status. */
+ gpif_acquiring = FALSE;
+}
+
+static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay)
+{
+ /*
+ * DELAY
+ * Delay cmd->sample_delay clocks.
+ */
+ pSTATE[0] = delay;
+
+ /*
+ * OPCODE
+ * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
+ * Collect data in this state.
+ */
+ pSTATE[8] = 0x00;
+
+ /*
+ * OUTPUT
+ * OE[0:3]=0, CTL[0:3]=0
+ */
+ pSTATE[16] = 0x00;
+
+ /*
+ * LOGIC FUNCTION
+ * Not used.
+ */
+ pSTATE[24] = 0x00;
+}
+
+static void gpid_make_data_dp_state(volatile BYTE *pSTATE)
+{
+ /*
+ * BRANCH
+ * Branch to IDLE if condition is true, back to S0 otherwise.
+ */
+ pSTATE[0] = (7 << 3) | (0 << 0);
+
+ /*
+ * OPCODE
+ * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
+ */
+ pSTATE[8] = (1 << 1) | (1 << 0);
+
+ /*
+ * OUTPUT
+ * OE[0:3]=0, CTL[0:3]=0
+ */
+ pSTATE[16] = 0x00;
+
+ /*
+ * LOGIC FUNCTION
+ * Evaluate if the FIFO full flag is set.
+ * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
+ */
+ pSTATE[24] = (6 << 3) | (6 << 0);
}
-void gpif_acquisition_start(void)
+bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
{
+ int i;
+ volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
+
+ /* Ensure GPIF is idle before reconfiguration. */
+ while (!(GPIFTRIG & 0x80));
+
+ /* Configure the EP2 FIFO. */
+ if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) {
+ EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
+ } else {
+ EP2FIFOCFG = bmAUTOIN;
+ }
+ SYNCDELAY();
+
+ /* Set IFCONFIG to the correct clock source. */
+ if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
+ IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ } else {
+ IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ }
+
+ /* Populate delay states. */
+ if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
+ cmd->sample_delay_h >= 6)
+ return false;
+
+ for (i = 0; i < cmd->sample_delay_h; i++)
+ gpif_make_delay_state(pSTATE++, 0);
+
+ if (cmd->sample_delay_l != 0)
+ gpif_make_delay_state(pSTATE++, cmd->sample_delay_l);
+
+ /* Populate S1 - the decision point. */
+ gpid_make_data_dp_state(pSTATE++);
+
+ /* Execute the whole GPIF waveform once. */
+ gpif_set_tc16(1);
+
/* Perform the initial GPIF read. */
gpif_fifo_read(GPIF_EP2);
+
+ /* Update the status. */
+ gpif_acquiring = TRUE;
+
+ return true;
+}
+
+void gpif_poll(void)
+{
+ /* Detect if acquisition has completed. */
+ if (gpif_acquiring && (GPIFTRIG & 0x80)) {
+ /* Activate NAK-ALL to avoid race conditions. */
+ FIFORESET = 0x80;
+ SYNCDELAY();
+
+ /* Switch to manual mode. */
+ EP2FIFOCFG = 0;
+ SYNCDELAY();
+
+ /* Reset EP2. */
+ FIFORESET = 0x02;
+ SYNCDELAY();
+
+ /* Return to auto mode. */
+ EP2FIFOCFG = bmAUTOIN;
+ SYNCDELAY();
+
+ /* Release NAK-ALL. */
+ FIFORESET = 0x00;
+ SYNCDELAY();
+
+ gpif_acquiring = FALSE;
+ }
}
projects / sigrok-firmware-fx2lafw.git / blobdiff