/*
- * This file is part of the fx2lafw project.
+ * This file is part of the sigrok-firmware-fx2lafw project.
*
* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>
-
#include <fx2lafw.h>
#include <gpif-acquisition.h>
+__bit gpif_acquiring;
+
static void gpif_reset_waveforms(void)
{
int i;
/* When GPIF is idle, tri-state the data bus. */
/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
- GPIFIDLECS = (1 << 0);
+ GPIFIDLECS = (0 << 0);
/* When GPIF is idle, set CTL0-CTL5 to 0. */
GPIFIDLECTL = 0;
/* Contains RDY* pin values. Read-only according to TRM. */
GPIFREADYSTAT = 0;
+
+ /* Make GPIF stop on transaction count not flag. */
+ EP2GPIFPFSTOP = (0 << 0);
}
static void gpif_init_addr_pins(void)
/* Initialize flowstate registers (not used by us). */
gpif_init_flowstates();
+
+ /* Reset the status. */
+ gpif_acquiring = FALSE;
}
-void gpif_acquisition_start(void)
+static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t opcode, uint8_t output)
{
- xdata volatile BYTE *pSTATE;
+ /*
+ * DELAY
+ * Delay cmd->sample_delay clocks.
+ */
+ pSTATE[0] = delay;
- /* GPIF terminology: DP = decision point, NDP = non-decision-point */
+ /*
+ * OPCODE
+ * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
+ * Collect data in this state.
+ */
+ pSTATE[8] = opcode;
- /* Populate WAVEDATA
- *
- * This is the basic algorithm implemented in our GPIF state machine:
- *
- * State 0: NDP: Sample the FIFO data bus.
- * State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
- * end the current waveform. Otherwise, go to state 0 again,
- * i.e., sample data until EP2 is full.
- * State 2: Unused.
- * State 3: Unused.
- * State 4: Unused.
- * State 5: Unused.
- * State 6: Unused.
+ /*
+ * OUTPUT
+ * OE[0:3]=0, CTL[0:3]=0
*/
+ pSTATE[16] = output;
- /* Populate S0 */
- pSTATE = &GPIF_WAVE_DATA;
- pSTATE[0] = 0x01;
- pSTATE[8] = 0x02;
- pSTATE[16] = 0x00;
+ /*
+ * LOGIC FUNCTION
+ * Not used.
+ */
pSTATE[24] = 0x00;
+}
- /* Populate S1 */
- pSTATE = &GPIF_WAVE_DATA + 1;
- pSTATE[0] = 0x00;
- pSTATE[8] = 0x01;
- pSTATE[16] = 0x00;
- pSTATE[24] = 0x36;
+static void gpid_make_data_dp_state(volatile BYTE *pSTATE)
+{
+ /*
+ * BRANCH
+ * Branch to IDLE if condition is true, back to S0 otherwise.
+ */
+ pSTATE[0] = (7 << 3) | (0 << 0);
- /* Populate Reserved Words */
- pSTATE = &GPIF_WAVE_DATA + 7;
- pSTATE[0] = 0x07;
- pSTATE[8] = 0x00;
+ /*
+ * OPCODE
+ * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
+ */
+ pSTATE[8] = (1 << 1) | (1 << 0);
+
+ /*
+ * OUTPUT
+ * OE[0:3]=0, CTL[0:3]=0
+ */
pSTATE[16] = 0x00;
- pSTATE[24] = 0x3f;
+ /*
+ * LOGIC FUNCTION
+ * Evaluate if the FIFO full flag is set.
+ * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
+ */
+ pSTATE[24] = (6 << 3) | (6 << 0);
+}
+
+bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
+{
+ int i;
+ volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
+
+ /* Ensure GPIF is idle before reconfiguration. */
+ while (!(GPIFTRIG & 0x80));
+
+ /* Configure the EP2 FIFO. */
+ if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) {
+ EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
+ } else {
+ EP2FIFOCFG = bmAUTOIN;
+ }
SYNCDELAY();
+ /* Set IFCONFIG to the correct clock source. */
+ if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
+ IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ } else {
+ IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ }
+
+ if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
+ uint8_t delay_1, delay_2;
+
+ /* We need a pulse where the CTL2 pin alternates states. */
+
+ /* Make the low pulse shorter then the high pulse. */
+ delay_2 = cmd->sample_delay_l >> 2;
+ /* Work around >12MHz case resulting in a 0 delay low pulse. */
+ if (delay_2 == 0)
+ delay_2 = 1;
+ delay_1 = cmd->sample_delay_l - delay_2;
+
+ gpif_make_delay_state(pSTATE++, delay_2, 0x00, 0x40);
+ gpif_make_delay_state(pSTATE++, delay_1, 0x00, 0x46);
+ } else {
+ /* Populate delay states. */
+ if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
+ cmd->sample_delay_h >= 6)
+ return false;
+
+ for (i = 0; i < cmd->sample_delay_h; i++)
+ gpif_make_delay_state(pSTATE++, 0, 0x00, 0x00);
+
+ if (cmd->sample_delay_l != 0)
+ gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00, 0x00);
+ }
+
+ /* Populate S1 - the decision point. */
+ gpid_make_data_dp_state(pSTATE++);
+
+ /* Execute the whole GPIF waveform once. */
+ gpif_set_tc16(1);
+
/* Perform the initial GPIF read. */
gpif_fifo_read(GPIF_EP2);
+
+ /* Update the status. */
+ gpif_acquiring = TRUE;
+
+ return true;
+}
+
+void gpif_poll(void)
+{
+ /* Detect if acquisition has completed. */
+ if (gpif_acquiring && (GPIFTRIG & 0x80)) {
+ /* Activate NAK-ALL to avoid race conditions. */
+ FIFORESET = 0x80;
+ SYNCDELAY();
+
+ /* Switch to manual mode. */
+ EP2FIFOCFG = 0;
+ SYNCDELAY();
+
+ /* Reset EP2. */
+ FIFORESET = 0x02;
+ SYNCDELAY();
+
+ /* Return to auto mode. */
+ EP2FIFOCFG = bmAUTOIN;
+ SYNCDELAY();
+
+ /* Release NAK-ALL. */
+ FIFORESET = 0x00;
+ SYNCDELAY();
+
+ gpif_acquiring = FALSE;
+ }
}
projects / sigrok-firmware-fx2lafw.git / blobdiff