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1 | /* | |
2 | * This file is part of the sigrok-firmware-fx2lafw project. | |
3 | * | |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
22 | * | |
23 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
24 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
25 | * | |
26 | * Technical notes: | |
27 | * | |
28 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
29 | * - We use the internal 48MHz clock for GPIF. | |
30 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7, | |
31 | * or PB0-PB7 + PD0-PD7 for 16-channel sampling. | |
32 | * - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host. | |
33 | * | |
34 | * Documentation: | |
35 | * | |
36 | * - See http://sigrok.org/wiki/Fx2lafw | |
37 | */ | |
38 | ||
39 | #include <fx2regs.h> | |
40 | #include <fx2macros.h> | |
41 | #include <fx2ints.h> | |
42 | #include <delay.h> | |
43 | #include <setupdat.h> | |
44 | #include <eputils.h> | |
45 | #include <gpif.h> | |
46 | #include <command.h> | |
47 | #include <fx2lafw.h> | |
48 | #include <gpif-acquisition.h> | |
49 | ||
50 | /* ... */ | |
51 | volatile __bit got_sud; | |
52 | BYTE vendor_command; | |
53 | ||
54 | volatile WORD ledcounter = 0; | |
55 | ||
56 | static void setup_endpoints(void) | |
57 | { | |
58 | /* Setup EP2 (IN). */ | |
59 | EP2CFG = (1u << 7) | /* EP is valid/activated */ | |
60 | (1u << 6) | /* EP direction: IN */ | |
61 | (1u << 5) | (0u << 4) | /* EP Type: bulk */ | |
62 | (1u << 3) | /* EP buffer size: 1024 */ | |
63 | (0u << 2) | /* Reserved. */ | |
64 | (0u << 1) | (0u << 0); /* EP buffering: quad buffering */ | |
65 | SYNCDELAY(); | |
66 | ||
67 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ | |
68 | EP1INCFG &= ~bmVALID; | |
69 | SYNCDELAY(); | |
70 | EP1OUTCFG &= ~bmVALID; | |
71 | SYNCDELAY(); | |
72 | EP4CFG &= ~bmVALID; | |
73 | SYNCDELAY(); | |
74 | EP6CFG &= ~bmVALID; | |
75 | SYNCDELAY(); | |
76 | EP8CFG &= ~bmVALID; | |
77 | SYNCDELAY(); | |
78 | ||
79 | /* EP2: Reset the FIFOs. */ | |
80 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
81 | RESETFIFO(0x02); | |
82 | ||
83 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ | |
84 | EP2FIFOCFG = bmAUTOIN; | |
85 | SYNCDELAY(); | |
86 | ||
87 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
88 | EP2AUTOINLENH = 0x02; | |
89 | SYNCDELAY(); | |
90 | EP2AUTOINLENL = 0x00; | |
91 | SYNCDELAY(); | |
92 | ||
93 | /* EP2: Set the GPIF flag to 'full'. */ | |
94 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); | |
95 | SYNCDELAY(); | |
96 | } | |
97 | ||
98 | static void send_fw_version(void) | |
99 | { | |
100 | /* Populate the buffer. */ | |
101 | struct version_info *const vi = (struct version_info *)EP0BUF; | |
102 | vi->major = FX2LAFW_VERSION_MAJOR; | |
103 | vi->minor = FX2LAFW_VERSION_MINOR; | |
104 | ||
105 | /* Send the message. */ | |
106 | EP0BCH = 0; | |
107 | SYNCDELAY(); | |
108 | EP0BCL = sizeof(struct version_info); | |
109 | SYNCDELAY(); | |
110 | } | |
111 | ||
112 | static void send_revid_version(void) | |
113 | { | |
114 | uint8_t *p; | |
115 | ||
116 | /* Populate the buffer. */ | |
117 | p = (uint8_t *)EP0BUF; | |
118 | *p = REVID; | |
119 | ||
120 | /* Send the message. */ | |
121 | EP0BCH = 0; | |
122 | SYNCDELAY(); | |
123 | EP0BCL = 1; | |
124 | SYNCDELAY(); | |
125 | } | |
126 | ||
127 | BOOL handle_vendorcommand(BYTE cmd) | |
128 | { | |
129 | /* Protocol implementation */ | |
130 | switch (cmd) { | |
131 | case CMD_START: | |
132 | /* Tell hardware we are ready to receive data. */ | |
133 | vendor_command = cmd; | |
134 | EP0BCL = 0; | |
135 | SYNCDELAY(); | |
136 | return TRUE; | |
137 | case CMD_GET_FW_VERSION: | |
138 | send_fw_version(); | |
139 | return TRUE; | |
140 | case CMD_GET_REVID_VERSION: | |
141 | send_revid_version(); | |
142 | return TRUE; | |
143 | } | |
144 | ||
145 | return FALSE; | |
146 | } | |
147 | ||
148 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
149 | { | |
150 | /* We only support interface 0, alternate interface 0. */ | |
151 | if (ifc != 0) | |
152 | return FALSE; | |
153 | ||
154 | *alt_ifc = 0; | |
155 | return TRUE; | |
156 | } | |
157 | ||
158 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
159 | { | |
160 | /* We only support interface 0, alternate interface 0. */ | |
161 | if (ifc != 0 || alt_ifc != 0) | |
162 | return FALSE; | |
163 | ||
164 | /* Perform procedure from TRM, section 2.3.7: */ | |
165 | ||
166 | /* (1) TODO. */ | |
167 | ||
168 | /* (2) Reset data toggles of the EPs in the interface. */ | |
169 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
170 | RESETTOGGLE(0x82); | |
171 | ||
172 | /* (3) Restore EPs to their default conditions. */ | |
173 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
174 | RESETFIFO(0x02); | |
175 | /* TODO */ | |
176 | ||
177 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ | |
178 | ||
179 | return TRUE; | |
180 | } | |
181 | ||
182 | BYTE handle_get_configuration(void) | |
183 | { | |
184 | /* We only support configuration 1. */ | |
185 | return 1; | |
186 | } | |
187 | ||
188 | BOOL handle_set_configuration(BYTE cfg) | |
189 | { | |
190 | /* We only support configuration 1. */ | |
191 | return (cfg == 1) ? TRUE : FALSE; | |
192 | } | |
193 | ||
194 | void sudav_isr(void) __interrupt(SUDAV_ISR) | |
195 | { | |
196 | got_sud = TRUE; | |
197 | CLEAR_SUDAV(); | |
198 | } | |
199 | ||
200 | /* IN BULK NAK - the host started requesting data. */ | |
201 | void ibn_isr(void) __interrupt(IBN_ISR) | |
202 | { | |
203 | /* | |
204 | * If the IBN interrupt is not disabled, clearing | |
205 | * does not work. See AN78446, 6.2. | |
206 | */ | |
207 | BYTE ibnsave = IBNIE; | |
208 | IBNIE = 0; | |
209 | CLEAR_USBINT(); | |
210 | ||
211 | /* | |
212 | * If the host sent the START command, start the GPIF | |
213 | * engine. The host will repeat the BULK IN in the next | |
214 | * microframe. | |
215 | */ | |
216 | if ((IBNIRQ & bmEP2IBN) && (gpif_acquiring == PREPARED)) { | |
217 | ledcounter = 1; | |
218 | LED_OFF(); | |
219 | gpif_acquisition_start(); | |
220 | } | |
221 | ||
222 | /* Clear IBN flags for all EPs. */ | |
223 | IBNIRQ = 0xff; | |
224 | ||
225 | NAKIRQ = bmIBN; | |
226 | SYNCDELAY(); | |
227 | ||
228 | IBNIE = ibnsave; | |
229 | SYNCDELAY(); | |
230 | } | |
231 | ||
232 | void usbreset_isr(void) __interrupt(USBRESET_ISR) | |
233 | { | |
234 | handle_hispeed(FALSE); | |
235 | CLEAR_USBRESET(); | |
236 | } | |
237 | ||
238 | void hispeed_isr(void) __interrupt(HISPEED_ISR) | |
239 | { | |
240 | handle_hispeed(TRUE); | |
241 | CLEAR_HISPEED(); | |
242 | } | |
243 | ||
244 | void timer2_isr(void) __interrupt(TF2_ISR) | |
245 | { | |
246 | /* Blink LED during acquisition, keep it on otherwise. */ | |
247 | if (gpif_acquiring == RUNNING) { | |
248 | if (--ledcounter == 0) { | |
249 | LED_TOGGLE(); | |
250 | ledcounter = 1000; | |
251 | } | |
252 | } else if (gpif_acquiring == STOPPED) { | |
253 | LED_ON(); | |
254 | } | |
255 | TF2 = 0; | |
256 | } | |
257 | ||
258 | void fx2lafw_init(void) | |
259 | { | |
260 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
261 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; | |
262 | ||
263 | got_sud = FALSE; | |
264 | vendor_command = 0; | |
265 | ||
266 | /* Renumerate. */ | |
267 | RENUMERATE_UNCOND(); | |
268 | ||
269 | SETCPUFREQ(CLK_48M); | |
270 | ||
271 | USE_USB_INTS(); | |
272 | ||
273 | /* TODO: Does the order of the following lines matter? */ | |
274 | ENABLE_SUDAV(); | |
275 | ENABLE_EP2IBN(); | |
276 | ENABLE_HISPEED(); | |
277 | ENABLE_USBRESET(); | |
278 | ||
279 | LED_INIT(); | |
280 | LED_ON(); | |
281 | ||
282 | /* Init timer2. */ | |
283 | RCAP2L = -500 & 0xff; | |
284 | RCAP2H = (-500 & 0xff00) >> 8; | |
285 | T2CON = 0; | |
286 | ET2 = 1; | |
287 | TR2 = 1; | |
288 | ||
289 | /* Global (8051) interrupt enable. */ | |
290 | EA = 1; | |
291 | ||
292 | /* Setup the endpoints. */ | |
293 | setup_endpoints(); | |
294 | ||
295 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
296 | gpif_init_la(); | |
297 | } | |
298 | ||
299 | void fx2lafw_poll(void) | |
300 | { | |
301 | if (got_sud) { | |
302 | handle_setupdata(); | |
303 | got_sud = FALSE; | |
304 | } | |
305 | ||
306 | if (vendor_command) { | |
307 | switch (vendor_command) { | |
308 | case CMD_START: | |
309 | if ((EP0CS & bmEPBUSY) != 0) | |
310 | break; | |
311 | ||
312 | if (EP0BCL == sizeof(struct cmd_start_acquisition)) { | |
313 | gpif_acquisition_prepare( | |
314 | (const struct cmd_start_acquisition *)EP0BUF); | |
315 | } | |
316 | ||
317 | /* Acknowledge the vendor command. */ | |
318 | vendor_command = 0; | |
319 | break; | |
320 | default: | |
321 | /* Unimplemented command. */ | |
322 | vendor_command = 0; | |
323 | break; | |
324 | } | |
325 | } | |
326 | ||
327 | gpif_poll(); | |
328 | } | |
329 | ||
330 | void main(void) | |
331 | { | |
332 | fx2lafw_init(); | |
333 | while (1) | |
334 | fx2lafw_poll(); | |
335 | } |