projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e5f0cff PET |
1 | ------------------------------------------------------------------------------- |
| 2 | Maxim MAX7301 | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a set of example captures of a Maxim MAX7301 GPIO expander. | |
| 6 | ||
| 7 | Details: | |
| 8 | https://www.maximintegrated.com/en/products/MAX7301 | |
| 9 | ||
| 10 | ||
| 11 | Logic analyzer setup | |
| 12 | -------------------- | |
| 13 | ||
| 14 | The logic analyzer used was a Saleae Logic (at 24MHz): | |
| 15 | ||
| 16 | Probe MAX7301 | |
| 17 | ------------------- | |
| 18 | 0 CS# | |
| 19 | 1 MOSI | |
| 20 | 2 CLK | |
| 21 | 3 MISO | |
| 22 | 4 P12 | |
| 23 | 5 P13 | |
| 24 | 6 P14 | |
| 25 | 7 P15 | |
| 26 | ||
| 27 | ||
| 28 | Data | |
| 29 | ---- | |
| 30 | ||
| 31 | The capture was generated using sigrok-cli. | |
| 32 | ||
| 33 | The chip was driven by a 1Bitsy STM32F415RGT6 development board and libopencm3 | |
| 34 | based driver firmware. | |
| 35 |