projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 4c90e08e UH |
1 | ------------------------------------------------------------------------------- |
| 2 | EDID | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 44d68352 SB |
5 | The captures in this directory were taken from the DDC/I2C bus. |
| 6 | ||
| 7 | For the two Samsung displays below, the logic analyzer was attached to a | |
| 8 | VGA cable, which connects the computer and the display while the EDID data | |
| 9 | was sent across the I2C bus. | |
| fe2f7efc BV |
10 | |
| 11 | To decode these, set up a protocol decoder stack like this: | |
| 12 | ||
| 44d68352 | 13 | i2c -> edid |
| fe2f7efc | 14 | |
| 4c90e08e UH |
15 | Details: |
| 16 | https://en.wikipedia.org/wiki/Extended_display_identification_data | |
| 17 | https://en.wikipedia.org/wiki/Display_Data_Channel | |
| 18 | ||
| 19 | ||
| 20 | samsung_le46b620r3p.sr / samsung_syncmaster245b.sr | |
| 21 | -------------------------------------------------- | |
| 22 | ||
| 47cd3c8f | 23 | The logic analyzer used was a Saleae Logic (at 500kHz): |
| 4c90e08e | 24 | |
| 47cd3c8f UH |
25 | Probe I2C pin |
| 26 | ------------------- | |
| 4c90e08e UH |
27 | 1 (black) SDA |
| 28 | 2 (brown) SCL | |
| 29 | ||
| 30 | ||
| 31 | samsung_syncmaster203b.sr | |
| 32 | ------------------------- | |
| 33 | ||
| 47cd3c8f | 34 | The logic analyzer used was a Saleae Logic (at 1MHz): |
| 4c90e08e | 35 | |
| 47cd3c8f UH |
36 | Probe I2C pin |
| 37 | ------------------- | |
| 4c90e08e UH |
38 | 1 (black) SCL |
| 39 | 2 (brown) SDA | |
| 40 | ||
| 44d68352 SB |
41 | |
| 42 | acer_al711_on_dp_dm_hdmi_vga.sr | |
| 43 | ------------------------------- | |
| 44 | ||
| 45 | This setup is somewhat more evolved, as it used a computer with a | |
| 46 | dual-mode displayport (DP++), a DP-HDMI (Type 1) adapter, a HDMI DDC | |
| 47 | breakout cable, a HDMI-VGA adapter, and a CRT screen with VGA input. | |
| 48 | ||
| 49 | The logic analyzer was connected to the DDC bus between the two adapters | |
| 50 | above, i.e. on the HDMI connection. As the DP-HDMI adapter uses a level | |
| 51 | shifter between DP and HDMI DDC busses, also the communication between | |
| 52 | computer and the DP adapter is visible (the DDC busses on both side are | |
| 53 | physically connected). The DP-HDMI adapter is visible at I2C address | |
| 54 | 0x40 and responds with the readonly identifier 'DP-HDMI Adaptor<EOT>'. | |
| 55 | ||
| 56 | The HDMI-VGA adapter modifies the EDID contents from the VGA moniter, | |
| 57 | it adds an CEA extension block at offset 0x80 and notifies the existence | |
| 58 | of the extension block in the first block. |