kingst-la2016: zero pad FPGA bitstream to 4KiB boundaries

[libsigrok.git] / src / hardware / kingst-la2016 / protocol.h

diff --git a/src/hardware/kingst-la2016/protocol.h b/src/hardware/kingst-la2016/protocol.h
index 5d465d942a094948c8fb301a09ddac369bbc16b8..dd1092446d06d6db15fa1c19007615b465a3fe11 100644 (file)
--- a/src/hardware/kingst-la2016/protocol.h
+++ b/src/hardware/kingst-la2016/protocol.h
@@ -67,7 +67,7 @@
  * The device expects some zero padding to follow the content of the
  * file which contains the FPGA bitstream. Specify the chunk size here.
  */
-#define LA2016_EP2_PADDING     2048
+#define LA2016_EP2_PADDING     4096
 
 /*
  * Whether the logic input threshold voltage is a config item of the