Always interleave analog data with all enabled probes.

[libsigrok.git] / hardware / rigol-ds1xx2 / protocol.c

diff --git a/hardware/rigol-ds1xx2/protocol.c b/hardware/rigol-ds1xx2/protocol.c
index e17cf215c749b975b57063efeff7fa8796c8fe44..6879a04c12a90e8c50bb7f81349baf1237ea1606 100644 (file)
--- a/hardware/rigol-ds1xx2/protocol.c
+++ b/hardware/rigol-ds1xx2/protocol.c
@@ -49,6 +49,7 @@ SR_PRIV int rigol_ds1xx2_receive_data(int fd, int revents, void *cb_data)
                        return TRUE;
                for (i = 0; i < len; i++)
                        data[i] = devc->scale / 25.6 * (128 - buf[i]) - devc->offset;
+               analog.probes = devc->enabled_probes;
                analog.num_samples = len;
                analog.data = data;
                analog.mq = SR_MQ_VOLTAGE;