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Introduce standard implementation of the dev_list() callback
[libsigrok.git] / src / hardware / rigol-ds / api.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <config.h>
23#include <fcntl.h>
24#include <unistd.h>
25#include <stdlib.h>
26#include <string.h>
27#include <strings.h>
28#include <math.h>
29#include <glib.h>
30#include <libsigrok/libsigrok.h>
31#include "libsigrok-internal.h"
32#include "scpi.h"
33#include "protocol.h"
34
35static const uint32_t scanopts[] = {
36 SR_CONF_CONN,
37 SR_CONF_SERIALCOMM
38};
39
40static const uint32_t devopts[] = {
41 SR_CONF_OSCILLOSCOPE,
42 SR_CONF_LIMIT_FRAMES | SR_CONF_SET,
43 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
44 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
45 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
47 SR_CONF_NUM_HDIV | SR_CONF_GET,
48 SR_CONF_SAMPLERATE | SR_CONF_GET,
49 SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
50};
51
52static const uint32_t analog_devopts[] = {
53 SR_CONF_NUM_VDIV | SR_CONF_GET,
54 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
55 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
56};
57
58static const uint64_t timebases[][2] = {
59 /* nanoseconds */
60 { 1, 1000000000 },
61 { 2, 1000000000 },
62 { 5, 1000000000 },
63 { 10, 1000000000 },
64 { 20, 1000000000 },
65 { 50, 1000000000 },
66 { 100, 1000000000 },
67 { 500, 1000000000 },
68 /* microseconds */
69 { 1, 1000000 },
70 { 2, 1000000 },
71 { 5, 1000000 },
72 { 10, 1000000 },
73 { 20, 1000000 },
74 { 50, 1000000 },
75 { 100, 1000000 },
76 { 200, 1000000 },
77 { 500, 1000000 },
78 /* milliseconds */
79 { 1, 1000 },
80 { 2, 1000 },
81 { 5, 1000 },
82 { 10, 1000 },
83 { 20, 1000 },
84 { 50, 1000 },
85 { 100, 1000 },
86 { 200, 1000 },
87 { 500, 1000 },
88 /* seconds */
89 { 1, 1 },
90 { 2, 1 },
91 { 5, 1 },
92 { 10, 1 },
93 { 20, 1 },
94 { 50, 1 },
95 { 100, 1 },
96 { 200, 1 },
97 { 500, 1 },
98 { 1000, 1 },
99};
100
101static const uint64_t vdivs[][2] = {
102 /* microvolts */
103 { 500, 1000000 },
104 /* millivolts */
105 { 1, 1000 },
106 { 2, 1000 },
107 { 5, 1000 },
108 { 10, 1000 },
109 { 20, 1000 },
110 { 50, 1000 },
111 { 100, 1000 },
112 { 200, 1000 },
113 { 500, 1000 },
114 /* volts */
115 { 1, 1 },
116 { 2, 1 },
117 { 5, 1 },
118 { 10, 1 },
119 { 20, 1 },
120 { 50, 1 },
121 { 100, 1 },
122};
123
124#define NUM_TIMEBASE ARRAY_SIZE(timebases)
125#define NUM_VDIV ARRAY_SIZE(vdivs)
126
127static const char *trigger_sources[] = {
128 "CH1",
129 "CH2",
130 "CH3",
131 "CH4",
132 "EXT",
133 "AC Line",
134 "D0",
135 "D1",
136 "D2",
137 "D3",
138 "D4",
139 "D5",
140 "D6",
141 "D7",
142 "D8",
143 "D9",
144 "D10",
145 "D11",
146 "D12",
147 "D13",
148 "D14",
149 "D15",
150};
151
152static const char *trigger_slopes[] = {
153 "r",
154 "f",
155};
156
157static const char *coupling[] = {
158 "AC",
159 "DC",
160 "GND",
161};
162
163/* Do not change the order of entries */
164static const char *data_sources[] = {
165 "Live",
166 "Memory",
167 "Segmented",
168};
169
170enum vendor {
171 RIGOL,
172 AGILENT,
173};
174
175enum series {
176 VS5000,
177 DS1000,
178 DS2000,
179 DS2000A,
180 DSO1000,
181 DS1000Z,
182};
183
184/* short name, full name */
185static const struct rigol_ds_vendor supported_vendors[] = {
186 [RIGOL] = {"Rigol", "Rigol Technologies"},
187 [AGILENT] = {"Agilent", "Agilent Technologies"},
188};
189
190#define VENDOR(x) &supported_vendors[x]
191/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
192 * live waveform samples, memory buffer samples */
193static const struct rigol_ds_series supported_series[] = {
194 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
195 {50, 1}, {2, 1000}, 14, 2048, 0},
196 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
197 {50, 1}, {2, 1000}, 12, 600, 1048576},
198 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
199 {500, 1}, {500, 1000000}, 14, 1400, 14000},
200 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
201 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
202 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
203 {50, 1}, {2, 1000}, 12, 600, 20480},
204 [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
205 {50, 1}, {1, 1000}, 12, 1200, 12000000},
206};
207
208#define SERIES(x) &supported_series[x]
209/* series, model, min timebase, analog channels, digital */
210static const struct rigol_ds_model supported_models[] = {
211 {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
212 {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
213 {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
214 {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
215 {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
216 {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
217 {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
218 {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
219 {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
220 {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
221 {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
222 {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
223 {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
224 {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
225 {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
226 {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
227 {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
228 {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
229 {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
230 {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
231 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
232 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
233 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
234 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
235 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
236 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
237 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
238 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
239 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
240 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
241 {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false},
242 {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false},
243 {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
244 {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
245 {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
246 {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
247 {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
248 {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
249 {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true},
250};
251
252SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
253
254static void clear_helper(void *priv)
255{
256 struct dev_context *devc;
257 unsigned int i;
258
259 devc = priv;
260 g_free(devc->data);
261 g_free(devc->buffer);
262 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
263 g_free(devc->coupling[i]);
264 g_free(devc->trigger_source);
265 g_free(devc->trigger_slope);
266 g_free(devc->analog_groups);
267 g_free(devc);
268}
269
270static int dev_clear(const struct sr_dev_driver *di)
271{
272 return std_dev_clear(di, clear_helper);
273}
274
275static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
276{
277 return std_init(sr_ctx, di, LOG_PREFIX);
278}
279
280static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
281{
282 struct dev_context *devc;
283 struct sr_dev_inst *sdi;
284 struct sr_scpi_hw_info *hw_info;
285 struct sr_channel *ch;
286 long n[3];
287 unsigned int i;
288 const struct rigol_ds_model *model = NULL;
289 gchar *channel_name, **version;
290
291 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
292 sr_info("Couldn't get IDN response, retrying.");
293 sr_scpi_close(scpi);
294 sr_scpi_open(scpi);
295 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
296 sr_info("Couldn't get IDN response.");
297 return NULL;
298 }
299 }
300
301 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
302 if (!g_ascii_strcasecmp(hw_info->manufacturer,
303 supported_models[i].series->vendor->full_name) &&
304 !strcmp(hw_info->model, supported_models[i].name)) {
305 model = &supported_models[i];
306 break;
307 }
308 }
309
310 if (!model) {
311 sr_scpi_hw_info_free(hw_info);
312 return NULL;
313 }
314
315 sdi = g_malloc0(sizeof(struct sr_dev_inst));
316 sdi->vendor = g_strdup(model->series->vendor->name);
317 sdi->model = g_strdup(model->name);
318 sdi->version = g_strdup(hw_info->firmware_version);
319 sdi->conn = scpi;
320 sdi->driver = &rigol_ds_driver_info;
321 sdi->inst_type = SR_INST_SCPI;
322 sdi->serial_num = g_strdup(hw_info->serial_number);
323 devc = g_malloc0(sizeof(struct dev_context));
324 devc->limit_frames = 0;
325 devc->model = model;
326 devc->format = model->series->format;
327
328 /* DS1000 models with firmware before 0.2.4 used the old data format. */
329 if (model->series == SERIES(DS1000)) {
330 version = g_strsplit(hw_info->firmware_version, ".", 0);
331 do {
332 if (!version[0] || !version[1] || !version[2])
333 break;
334 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
335 break;
336 for (i = 0; i < 3; i++) {
337 if (sr_atol(version[i], &n[i]) != SR_OK)
338 break;
339 }
340 if (i != 3)
341 break;
342 scpi->firmware_version = n[0] * 100 + n[1] * 10 + n[2];
343 if (scpi->firmware_version < 24) {
344 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
345 devc->format = FORMAT_RAW;
346 }
347 break;
348 } while (0);
349 g_strfreev(version);
350 }
351
352 sr_scpi_hw_info_free(hw_info);
353
354 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
355 model->analog_channels);
356
357 for (i = 0; i < model->analog_channels; i++) {
358 channel_name = g_strdup_printf("CH%d", i + 1);
359 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
360
361 devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
362
363 devc->analog_groups[i]->name = channel_name;
364 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
365 sdi->channel_groups = g_slist_append(sdi->channel_groups,
366 devc->analog_groups[i]);
367 }
368
369 if (devc->model->has_digital) {
370 devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
371
372 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
373 channel_name = g_strdup_printf("D%d", i);
374 ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
375 g_free(channel_name);
376 devc->digital_group->channels = g_slist_append(
377 devc->digital_group->channels, ch);
378 }
379 devc->digital_group->name = g_strdup("LA");
380 sdi->channel_groups = g_slist_append(sdi->channel_groups,
381 devc->digital_group);
382 }
383
384 for (i = 0; i < NUM_TIMEBASE; i++) {
385 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
386 devc->timebases = &timebases[i];
387 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
388 devc->num_timebases = &timebases[i] - devc->timebases + 1;
389 }
390
391 for (i = 0; i < NUM_VDIV; i++) {
392 if (!memcmp(&devc->model->series->min_vdiv,
393 &vdivs[i], sizeof(uint64_t[2]))) {
394 devc->vdivs = &vdivs[i];
395 devc->num_vdivs = NUM_VDIV - i;
396 }
397 }
398
399 devc->buffer = g_malloc(ACQ_BUFFER_SIZE);
400 devc->data = g_malloc(ACQ_BUFFER_SIZE * sizeof(float));
401
402 devc->data_source = DATA_SOURCE_LIVE;
403
404 sdi->priv = devc;
405
406 return sdi;
407}
408
409static GSList *scan(struct sr_dev_driver *di, GSList *options)
410{
411 return sr_scpi_scan(di->context, options, probe_device);
412}
413
414static int dev_open(struct sr_dev_inst *sdi)
415{
416 int ret;
417 struct sr_scpi_dev_inst *scpi = sdi->conn;
418
419 if ((ret = sr_scpi_open(scpi)) < 0) {
420 sr_err("Failed to open SCPI device: %s.", sr_strerror(ret));
421 return SR_ERR;
422 }
423
424 if ((ret = rigol_ds_get_dev_cfg(sdi)) < 0) {
425 sr_err("Failed to get device config: %s.", sr_strerror(ret));
426 return SR_ERR;
427 }
428
429 sdi->status = SR_ST_ACTIVE;
430
431 return SR_OK;
432}
433
434static int dev_close(struct sr_dev_inst *sdi)
435{
436 struct sr_scpi_dev_inst *scpi;
437 struct dev_context *devc;
438
439 if (sdi->status != SR_ST_ACTIVE)
440 return SR_ERR_DEV_CLOSED;
441
442 scpi = sdi->conn;
443 devc = sdi->priv;
444
445 if (devc->model->series->protocol == PROTOCOL_V2)
446 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
447
448 if (scpi) {
449 if (sr_scpi_close(scpi) < 0)
450 return SR_ERR;
451 sdi->status = SR_ST_INACTIVE;
452 }
453
454 return SR_OK;
455}
456
457static int analog_frame_size(const struct sr_dev_inst *sdi)
458{
459 struct dev_context *devc = sdi->priv;
460 struct sr_channel *ch;
461 int analog_channels = 0;
462 GSList *l;
463
464 for (l = sdi->channels; l; l = l->next) {
465 ch = l->data;
466 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
467 analog_channels++;
468 }
469
470 if (analog_channels == 0)
471 return 0;
472
473 switch (devc->data_source) {
474 case DATA_SOURCE_LIVE:
475 return devc->model->series->live_samples;
476 case DATA_SOURCE_MEMORY:
477 return devc->model->series->buffer_samples / analog_channels;
478 default:
479 return 0;
480 }
481}
482
483static int digital_frame_size(const struct sr_dev_inst *sdi)
484{
485 struct dev_context *devc = sdi->priv;
486
487 switch (devc->data_source) {
488 case DATA_SOURCE_LIVE:
489 return devc->model->series->live_samples * 2;
490 case DATA_SOURCE_MEMORY:
491 return devc->model->series->buffer_samples * 2;
492 default:
493 return 0;
494 }
495}
496
497static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
498 const struct sr_channel_group *cg)
499{
500 struct dev_context *devc;
501 struct sr_channel *ch;
502 const char *tmp_str;
503 uint64_t samplerate;
504 int analog_channel = -1;
505 float smallest_diff = INFINITY;
506 int idx = -1;
507 unsigned i;
508
509 if (!sdi || !(devc = sdi->priv))
510 return SR_ERR_ARG;
511
512 /* If a channel group is specified, it must be a valid one. */
513 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
514 sr_err("Invalid channel group specified.");
515 return SR_ERR;
516 }
517
518 if (cg) {
519 ch = g_slist_nth_data(cg->channels, 0);
520 if (!ch)
521 return SR_ERR;
522 if (ch->type == SR_CHANNEL_ANALOG) {
523 if (ch->name[2] < '1' || ch->name[2] > '4')
524 return SR_ERR;
525 analog_channel = ch->name[2] - '1';
526 }
527 }
528
529 switch (key) {
530 case SR_CONF_NUM_HDIV:
531 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
532 break;
533 case SR_CONF_NUM_VDIV:
534 *data = g_variant_new_int32(devc->num_vdivs);
535 break;
536 case SR_CONF_DATA_SOURCE:
537 if (devc->data_source == DATA_SOURCE_LIVE)
538 *data = g_variant_new_string("Live");
539 else if (devc->data_source == DATA_SOURCE_MEMORY)
540 *data = g_variant_new_string("Memory");
541 else
542 *data = g_variant_new_string("Segmented");
543 break;
544 case SR_CONF_SAMPLERATE:
545 if (devc->data_source == DATA_SOURCE_LIVE) {
546 samplerate = analog_frame_size(sdi) /
547 (devc->timebase * devc->model->series->num_horizontal_divs);
548 *data = g_variant_new_uint64(samplerate);
549 } else {
550 sr_dbg("Unknown data source: %d.", devc->data_source);
551 return SR_ERR_NA;
552 }
553 break;
554 case SR_CONF_TRIGGER_SOURCE:
555 if (!strcmp(devc->trigger_source, "ACL"))
556 tmp_str = "AC Line";
557 else if (!strcmp(devc->trigger_source, "CHAN1"))
558 tmp_str = "CH1";
559 else if (!strcmp(devc->trigger_source, "CHAN2"))
560 tmp_str = "CH2";
561 else if (!strcmp(devc->trigger_source, "CHAN3"))
562 tmp_str = "CH3";
563 else if (!strcmp(devc->trigger_source, "CHAN4"))
564 tmp_str = "CH4";
565 else
566 tmp_str = devc->trigger_source;
567 *data = g_variant_new_string(tmp_str);
568 break;
569 case SR_CONF_TRIGGER_SLOPE:
570 if (!strncmp(devc->trigger_slope, "POS", 3)) {
571 tmp_str = "r";
572 } else if (!strncmp(devc->trigger_slope, "NEG", 3)) {
573 tmp_str = "f";
574 } else {
575 sr_dbg("Unknown trigger slope: '%s'.", devc->trigger_slope);
576 return SR_ERR_NA;
577 }
578 *data = g_variant_new_string(tmp_str);
579 break;
580 case SR_CONF_TIMEBASE:
581 for (i = 0; i < devc->num_timebases; i++) {
582 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
583 float diff = fabs(devc->timebase - tb);
584 if (diff < smallest_diff) {
585 smallest_diff = diff;
586 idx = i;
587 }
588 }
589 if (idx < 0) {
590 sr_dbg("Negative timebase index: %d.", idx);
591 return SR_ERR_NA;
592 }
593 *data = g_variant_new("(tt)", devc->timebases[idx][0],
594 devc->timebases[idx][1]);
595 break;
596 case SR_CONF_VDIV:
597 if (analog_channel < 0) {
598 sr_dbg("Negative analog channel: %d.", analog_channel);
599 return SR_ERR_NA;
600 }
601 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
602 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
603 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
604 if (diff < smallest_diff) {
605 smallest_diff = diff;
606 idx = i;
607 }
608 }
609 if (idx < 0) {
610 sr_dbg("Negative vdiv index: %d.", idx);
611 return SR_ERR_NA;
612 }
613 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
614 break;
615 case SR_CONF_COUPLING:
616 if (analog_channel < 0) {
617 sr_dbg("Negative analog channel: %d.", analog_channel);
618 return SR_ERR_NA;
619 }
620 *data = g_variant_new_string(devc->coupling[analog_channel]);
621 break;
622 default:
623 return SR_ERR_NA;
624 }
625
626 return SR_OK;
627}
628
629static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
630 const struct sr_channel_group *cg)
631{
632 struct dev_context *devc;
633 uint64_t p, q;
634 double t_dbl;
635 unsigned int i, j;
636 int ret;
637 const char *tmp_str;
638 char buffer[16];
639
640 if (!(devc = sdi->priv))
641 return SR_ERR_ARG;
642
643 if (sdi->status != SR_ST_ACTIVE)
644 return SR_ERR_DEV_CLOSED;
645
646 /* If a channel group is specified, it must be a valid one. */
647 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
648 sr_err("Invalid channel group specified.");
649 return SR_ERR;
650 }
651
652 ret = SR_OK;
653 switch (key) {
654 case SR_CONF_LIMIT_FRAMES:
655 devc->limit_frames = g_variant_get_uint64(data);
656 break;
657 case SR_CONF_TRIGGER_SLOPE:
658 tmp_str = g_variant_get_string(data, NULL);
659
660 if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r')) {
661 sr_err("Unknown trigger slope: '%s'.",
662 (tmp_str) ? tmp_str : "NULL");
663 return SR_ERR_ARG;
664 }
665
666 g_free(devc->trigger_slope);
667 devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG");
668 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
669 break;
670 case SR_CONF_HORIZ_TRIGGERPOS:
671 t_dbl = g_variant_get_double(data);
672 if (t_dbl < 0.0 || t_dbl > 1.0) {
673 sr_err("Invalid horiz. trigger position: %g.", t_dbl);
674 return SR_ERR;
675 }
676 devc->horiz_triggerpos = t_dbl;
677 /* We have the trigger offset as a percentage of the frame, but
678 * need to express this in seconds. */
679 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
680 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
681 ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
682 break;
683 case SR_CONF_TIMEBASE:
684 g_variant_get(data, "(tt)", &p, &q);
685 for (i = 0; i < devc->num_timebases; i++) {
686 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
687 devc->timebase = (float)p / q;
688 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
689 devc->timebase);
690 ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
691 break;
692 }
693 }
694 if (i == devc->num_timebases) {
695 sr_err("Invalid timebase index: %d.", i);
696 ret = SR_ERR_ARG;
697 }
698 break;
699 case SR_CONF_TRIGGER_SOURCE:
700 tmp_str = g_variant_get_string(data, NULL);
701 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
702 if (!strcmp(trigger_sources[i], tmp_str)) {
703 g_free(devc->trigger_source);
704 devc->trigger_source = g_strdup(trigger_sources[i]);
705 if (!strcmp(devc->trigger_source, "AC Line"))
706 tmp_str = "ACL";
707 else if (!strcmp(devc->trigger_source, "CH1"))
708 tmp_str = "CHAN1";
709 else if (!strcmp(devc->trigger_source, "CH2"))
710 tmp_str = "CHAN2";
711 else if (!strcmp(devc->trigger_source, "CH3"))
712 tmp_str = "CHAN3";
713 else if (!strcmp(devc->trigger_source, "CH4"))
714 tmp_str = "CHAN4";
715 else
716 tmp_str = (char *)devc->trigger_source;
717 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
718 break;
719 }
720 }
721 if (i == ARRAY_SIZE(trigger_sources)) {
722 sr_err("Invalid trigger source index: %d.", i);
723 ret = SR_ERR_ARG;
724 }
725 break;
726 case SR_CONF_VDIV:
727 if (!cg) {
728 sr_err("No channel group specified.");
729 return SR_ERR_CHANNEL_GROUP;
730 }
731 g_variant_get(data, "(tt)", &p, &q);
732 for (i = 0; i < devc->model->analog_channels; i++) {
733 if (cg == devc->analog_groups[i]) {
734 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
735 if (vdivs[j][0] != p || vdivs[j][1] != q)
736 continue;
737 devc->vdiv[i] = (float)p / q;
738 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
739 devc->vdiv[i]);
740 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
741 buffer);
742 }
743 sr_err("Invalid vdiv index: %d.", j);
744 return SR_ERR_ARG;
745 }
746 }
747 sr_dbg("Didn't set vdiv, unknown channel(group).");
748 return SR_ERR_NA;
749 case SR_CONF_COUPLING:
750 if (!cg) {
751 sr_err("No channel group specified.");
752 return SR_ERR_CHANNEL_GROUP;
753 }
754 tmp_str = g_variant_get_string(data, NULL);
755 for (i = 0; i < devc->model->analog_channels; i++) {
756 if (cg == devc->analog_groups[i]) {
757 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
758 if (!strcmp(tmp_str, coupling[j])) {
759 g_free(devc->coupling[i]);
760 devc->coupling[i] = g_strdup(coupling[j]);
761 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
762 devc->coupling[i]);
763 }
764 }
765 sr_err("Invalid coupling index: %d.", j);
766 return SR_ERR_ARG;
767 }
768 }
769 sr_dbg("Didn't set coupling, unknown channel(group).");
770 return SR_ERR_NA;
771 case SR_CONF_DATA_SOURCE:
772 tmp_str = g_variant_get_string(data, NULL);
773 if (!strcmp(tmp_str, "Live"))
774 devc->data_source = DATA_SOURCE_LIVE;
775 else if (devc->model->series->protocol >= PROTOCOL_V2
776 && !strcmp(tmp_str, "Memory"))
777 devc->data_source = DATA_SOURCE_MEMORY;
778 else if (devc->model->series->protocol >= PROTOCOL_V3
779 && !strcmp(tmp_str, "Segmented"))
780 devc->data_source = DATA_SOURCE_SEGMENTED;
781 else {
782 sr_err("Unknown data source: '%s'.", tmp_str);
783 return SR_ERR;
784 }
785 break;
786 default:
787 return SR_ERR_NA;
788 }
789
790 return ret;
791}
792
793static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
794 const struct sr_channel_group *cg)
795{
796 GVariant *tuple, *rational[2];
797 GVariantBuilder gvb;
798 unsigned int i;
799 struct dev_context *devc = NULL;
800
801 if (key == SR_CONF_SCAN_OPTIONS) {
802 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
803 scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
804 return SR_OK;
805 } else if (key == SR_CONF_DEVICE_OPTIONS && !cg) {
806 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
807 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
808 return SR_OK;
809 }
810
811 /* Every other option requires a valid device instance. */
812 if (!sdi || !(devc = sdi->priv))
813 return SR_ERR_ARG;
814
815 /* If a channel group is specified, it must be a valid one. */
816 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
817 sr_err("Invalid channel group specified.");
818 return SR_ERR;
819 }
820
821 switch (key) {
822 case SR_CONF_DEVICE_OPTIONS:
823 if (!cg) {
824 sr_err("No channel group specified.");
825 return SR_ERR_CHANNEL_GROUP;
826 }
827 if (cg == devc->digital_group) {
828 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
829 NULL, 0, sizeof(uint32_t));
830 return SR_OK;
831 } else {
832 for (i = 0; i < devc->model->analog_channels; i++) {
833 if (cg == devc->analog_groups[i]) {
834 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
835 analog_devopts, ARRAY_SIZE(analog_devopts), sizeof(uint32_t));
836 return SR_OK;
837 }
838 }
839 return SR_ERR_NA;
840 }
841 break;
842 case SR_CONF_COUPLING:
843 if (!cg) {
844 sr_err("No channel group specified.");
845 return SR_ERR_CHANNEL_GROUP;
846 }
847 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
848 break;
849 case SR_CONF_VDIV:
850 if (!devc)
851 /* Can't know this until we have the exact model. */
852 return SR_ERR_ARG;
853 if (!cg) {
854 sr_err("No channel group specified.");
855 return SR_ERR_CHANNEL_GROUP;
856 }
857 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
858 for (i = 0; i < devc->num_vdivs; i++) {
859 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
860 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
861 tuple = g_variant_new_tuple(rational, 2);
862 g_variant_builder_add_value(&gvb, tuple);
863 }
864 *data = g_variant_builder_end(&gvb);
865 break;
866 case SR_CONF_TIMEBASE:
867 if (!devc)
868 /* Can't know this until we have the exact model. */
869 return SR_ERR_ARG;
870 if (devc->num_timebases <= 0)
871 return SR_ERR_NA;
872 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
873 for (i = 0; i < devc->num_timebases; i++) {
874 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
875 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
876 tuple = g_variant_new_tuple(rational, 2);
877 g_variant_builder_add_value(&gvb, tuple);
878 }
879 *data = g_variant_builder_end(&gvb);
880 break;
881 case SR_CONF_TRIGGER_SOURCE:
882 if (!devc)
883 /* Can't know this until we have the exact model. */
884 return SR_ERR_ARG;
885 *data = g_variant_new_strv(trigger_sources,
886 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
887 break;
888 case SR_CONF_TRIGGER_SLOPE:
889 *data = g_variant_new_strv(trigger_slopes, ARRAY_SIZE(trigger_slopes));
890 break;
891 case SR_CONF_DATA_SOURCE:
892 if (!devc)
893 /* Can't know this until we have the exact model. */
894 return SR_ERR_ARG;
895 switch (devc->model->series->protocol) {
896 case PROTOCOL_V1:
897 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
898 break;
899 case PROTOCOL_V2:
900 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
901 break;
902 default:
903 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
904 break;
905 }
906 break;
907 default:
908 return SR_ERR_NA;
909 }
910
911 return SR_OK;
912}
913
914static int dev_acquisition_start(const struct sr_dev_inst *sdi)
915{
916 struct sr_scpi_dev_inst *scpi;
917 struct dev_context *devc;
918 struct sr_channel *ch;
919 struct sr_datafeed_packet packet;
920 gboolean some_digital;
921 GSList *l;
922
923 if (sdi->status != SR_ST_ACTIVE)
924 return SR_ERR_DEV_CLOSED;
925
926 scpi = sdi->conn;
927 devc = sdi->priv;
928
929 devc->num_frames = 0;
930
931 some_digital = FALSE;
932 for (l = sdi->channels; l; l = l->next) {
933 ch = l->data;
934 sr_dbg("handling channel %s", ch->name);
935 if (ch->type == SR_CHANNEL_ANALOG) {
936 if (ch->enabled)
937 devc->enabled_channels = g_slist_append(
938 devc->enabled_channels, ch);
939 if (ch->enabled != devc->analog_channels[ch->index]) {
940 /* Enabled channel is currently disabled, or vice versa. */
941 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
942 ch->enabled ? "ON" : "OFF") != SR_OK)
943 return SR_ERR;
944 devc->analog_channels[ch->index] = ch->enabled;
945 }
946 } else if (ch->type == SR_CHANNEL_LOGIC) {
947 /* Only one list entry for DS1000D series. All channels are retrieved
948 * together when this entry is processed. */
949 if (ch->enabled && (
950 devc->model->series->protocol > PROTOCOL_V2 ||
951 !some_digital))
952 devc->enabled_channels = g_slist_append(
953 devc->enabled_channels, ch);
954 if (ch->enabled) {
955 some_digital = TRUE;
956 /* Turn on LA module if currently off. */
957 if (!devc->la_enabled) {
958 if (rigol_ds_config_set(sdi,
959 devc->model->series->protocol >= PROTOCOL_V4 ?
960 ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
961 return SR_ERR;
962 devc->la_enabled = TRUE;
963 }
964 }
965 if (ch->enabled != devc->digital_channels[ch->index]) {
966 /* Enabled channel is currently disabled, or vice versa. */
967 if (rigol_ds_config_set(sdi,
968 devc->model->series->protocol >= PROTOCOL_V4 ?
969 ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index,
970 ch->enabled ? "ON" : "OFF") != SR_OK)
971 return SR_ERR;
972 devc->digital_channels[ch->index] = ch->enabled;
973 }
974 }
975 }
976
977 if (!devc->enabled_channels)
978 return SR_ERR;
979
980 /* Turn off LA module if on and no digital channels selected. */
981 if (devc->la_enabled && !some_digital)
982 if (rigol_ds_config_set(sdi,
983 devc->model->series->protocol >= PROTOCOL_V4 ?
984 ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
985 return SR_ERR;
986
987 /* Set memory mode. */
988 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
989 sr_err("Data source 'Segmented' not yet supported");
990 return SR_ERR;
991 }
992
993 devc->analog_frame_size = analog_frame_size(sdi);
994 devc->digital_frame_size = digital_frame_size(sdi);
995
996 switch (devc->model->series->protocol) {
997 case PROTOCOL_V2:
998 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
999 return SR_ERR;
1000 break;
1001 case PROTOCOL_V3:
1002 /* Apparently for the DS2000 the memory
1003 * depth can only be set in Running state -
1004 * this matches the behaviour of the UI. */
1005 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1006 return SR_ERR;
1007 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
1008 devc->analog_frame_size) != SR_OK)
1009 return SR_ERR;
1010 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
1011 return SR_ERR;
1012 break;
1013 default:
1014 break;
1015 }
1016
1017 if (devc->data_source == DATA_SOURCE_LIVE)
1018 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1019 return SR_ERR;
1020
1021 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
1022 rigol_ds_receive, (void *)sdi);
1023
1024 std_session_send_df_header(sdi, LOG_PREFIX);
1025
1026 devc->channel_entry = devc->enabled_channels;
1027
1028 if (rigol_ds_capture_start(sdi) != SR_OK)
1029 return SR_ERR;
1030
1031 /* Start of first frame. */
1032 packet.type = SR_DF_FRAME_BEGIN;
1033 sr_session_send(sdi, &packet);
1034
1035 return SR_OK;
1036}
1037
1038static int dev_acquisition_stop(struct sr_dev_inst *sdi)
1039{
1040 struct dev_context *devc;
1041 struct sr_scpi_dev_inst *scpi;
1042
1043 devc = sdi->priv;
1044
1045 if (sdi->status != SR_ST_ACTIVE) {
1046 sr_err("Device inactive, can't stop acquisition.");
1047 return SR_ERR;
1048 }
1049
1050 std_session_send_df_end(sdi, LOG_PREFIX);
1051
1052 g_slist_free(devc->enabled_channels);
1053 devc->enabled_channels = NULL;
1054 scpi = sdi->conn;
1055 sr_scpi_source_remove(sdi->session, scpi);
1056
1057 return SR_OK;
1058}
1059
1060SR_PRIV struct sr_dev_driver rigol_ds_driver_info = {
1061 .name = "rigol-ds",
1062 .longname = "Rigol DS",
1063 .api_version = 1,
1064 .init = init,
1065 .cleanup = std_cleanup,
1066 .scan = scan,
1067 .dev_list = std_dev_list,
1068 .dev_clear = dev_clear,
1069 .config_get = config_get,
1070 .config_set = config_set,
1071 .config_list = config_list,
1072 .dev_open = dev_open,
1073 .dev_close = dev_close,
1074 .dev_acquisition_start = dev_acquisition_start,
1075 .dev_acquisition_stop = dev_acquisition_stop,
1076 .context = NULL,
1077};
Hardware access and backend lib