]> sigrok.org Git - libsigrok.git/blame - src/hardware/sysclk-lwla/protocol.h
sysclk-lwla: Remove double USB set configuration
[libsigrok.git] / src / hardware / sysclk-lwla / protocol.h
CommitLineData
aeaad0b0
DE
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
21#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
22
5874e88d
DE
23#define LOG_PREFIX "sysclk-lwla"
24
5874e88d
DE
25#include <stdint.h>
26#include <glib.h>
c1aae900 27#include <libsigrok/libsigrok.h>
be64f90b 28#include <libsigrok-internal.h>
aeaad0b0 29
5874e88d 30#define VENDOR_NAME "SysClk"
5874e88d 31
be64f90b
DE
32/* Maximum configurable sample count limit.
33 * Due to compression, there is no meaningful hardware limit the driver
34 * could report. So this value is less than 2^64-1 for no reason other
35 * than to safeguard against integer overflows.
5874e88d 36 */
be64f90b 37#define MAX_LIMIT_SAMPLES (UINT64_C(1000) * 1000 * 1000 * 1000)
5874e88d 38
be64f90b
DE
39/* Maximum configurable acquisition time limit.
40 * Due to compression, there is no hardware limit that would be meaningful
41 * in practice. However, the LWLA1016 reports the elapsed time as a 32-bit
42 * value, so keep this below 2^32.
5874e88d 43 */
be64f90b 44#define MAX_LIMIT_MSEC (1000 * 1000 * 1000)
5874e88d 45
be64f90b 46struct acquisition_state;
5874e88d 47
be64f90b 48/* USB vendor and product IDs.
5874e88d 49 */
be64f90b
DE
50enum {
51 USB_VID_SYSCLK = 0x2961,
52 USB_PID_LWLA1016 = 0x6688,
53 USB_PID_LWLA1034 = 0x6689,
54};
29d58767 55
be64f90b 56/* USB device characteristics.
6358f0a9 57 */
be64f90b
DE
58enum {
59 USB_CONFIG = 1,
60 USB_INTERFACE = 0,
61 USB_TIMEOUT_MS = 3000,
6358f0a9
DE
62};
63
be64f90b 64/** LWLA1034 clock sources.
5874e88d
DE
65 */
66enum clock_source {
be64f90b 67 CLOCK_INTERNAL = 0,
6358f0a9 68 CLOCK_EXT_CLK,
5874e88d
DE
69};
70
be64f90b 71/** LWLA1034 trigger sources.
e6e54bd2
DE
72 */
73enum trigger_source {
74 TRIGGER_CHANNELS = 0,
75 TRIGGER_EXT_TRG,
76};
77
be64f90b 78/** Edge choices for the LWLA1034 external clock and trigger inputs.
e6e54bd2 79 */
6358f0a9
DE
80enum signal_edge {
81 EDGE_POSITIVE = 0,
82 EDGE_NEGATIVE,
e6e54bd2
DE
83};
84
be64f90b
DE
85/* Common indicator for no or unknown FPGA config. */
86enum {
87 FPGA_NOCONF = -1,
88};
89
90/** Acquisition protocol states.
5874e88d 91 */
be64f90b
DE
92enum protocol_state {
93 /* idle states */
5874e88d 94 STATE_IDLE = 0,
5874e88d 95 STATE_STATUS_WAIT,
be64f90b
DE
96 /* device command states */
97 STATE_START_CAPTURE,
5874e88d 98 STATE_STOP_CAPTURE,
5874e88d 99 STATE_READ_PREPARE,
be64f90b
DE
100 STATE_READ_FINISH,
101 /* command followed by response */
102 STATE_EXPECT_RESPONSE = 1 << 3,
103 STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE,
104 STATE_LENGTH_REQUEST,
5874e88d 105 STATE_READ_REQUEST,
5874e88d
DE
106};
107
108/** Private, per-device-instance driver context.
109 */
aeaad0b0 110struct dev_context {
be64f90b 111 uint64_t samplerate; /* requested samplerate */
29d58767 112
be64f90b
DE
113 uint64_t limit_msec; /* requested capture duration in ms */
114 uint64_t limit_samples; /* requested capture length in samples */
5874e88d 115
be64f90b 116 uint64_t channel_mask; /* bit mask of enabled channels */
5874e88d 117
be64f90b
DE
118 uint64_t trigger_mask; /* trigger enable mask */
119 uint64_t trigger_edge_mask; /* trigger type mask */
120 uint64_t trigger_values; /* trigger level/slope bits */
aeaad0b0 121
be64f90b
DE
122 const struct model_info *model; /* device model descriptor */
123 struct acquisition_state *acquisition; /* running capture state */
124 int active_fpga_config; /* FPGA configuration index */
aeaad0b0 125
be64f90b
DE
126 enum protocol_state state; /* async protocol state */
127 gboolean cancel_requested; /* stop after current transfer */
128 gboolean transfer_error; /* error during device communication */
aeaad0b0 129
be64f90b
DE
130 gboolean cfg_rle; /* RLE compression setting */
131 enum clock_source cfg_clock_source; /* clock source setting */
132 enum signal_edge cfg_clock_edge; /* ext clock edge setting */
133 enum trigger_source cfg_trigger_source; /* trigger source setting */
134 enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */
aeaad0b0 135
be64f90b 136};
6358f0a9 137
be64f90b
DE
138/** LWLA model descriptor.
139 */
140struct model_info {
141 char name[12];
142 int num_channels;
5874e88d 143
be64f90b
DE
144 unsigned int num_devopts;
145 uint32_t devopts[8];
e6e54bd2 146
be64f90b
DE
147 unsigned int num_samplerates;
148 uint64_t samplerates[20];
c81069b3 149
be64f90b
DE
150 int (*apply_fpga_config)(const struct sr_dev_inst *sdi);
151 int (*device_init_check)(const struct sr_dev_inst *sdi);
152 int (*setup_acquisition)(const struct sr_dev_inst *sdi);
5874e88d 153
be64f90b
DE
154 int (*prepare_request)(const struct sr_dev_inst *sdi);
155 int (*handle_response)(const struct sr_dev_inst *sdi);
aeaad0b0
DE
156};
157
be64f90b
DE
158SR_PRIV const struct model_info lwla1016_info;
159SR_PRIV const struct model_info lwla1034_info;
5874e88d 160
5874e88d 161SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
aeaad0b0 162
db24496a 163#endif