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Build: Include <config.h> first in all source files
[libsigrok.git] / src / hardware / pipistrello-ols / api.c
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4bd80e12 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
4bd80e12 21#include "protocol.h"
22
f254bc4b 23static const uint32_t devopts[] = {
4bd80e12 24 SR_CONF_LOGIC_ANALYZER,
5827f61b
BV		 25 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
26 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
27 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
28 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
29 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
30 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
31 SR_CONF_SWAP | SR_CONF_SET,
32 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
4bd80e12 33};
34
acc885c7
BV		 35static const int32_t trigger_matches[] = {
36 SR_TRIGGER_ZERO,
37 SR_TRIGGER_ONE,
38 SR_TRIGGER_RISING,
39 SR_TRIGGER_FALLING,
40};
41
4bd80e12 42#define STR_PATTERN_NONE "None"
43#define STR_PATTERN_EXTERNAL "External"
44#define STR_PATTERN_INTERNAL "Internal"
45
46/* Supported methods of test pattern outputs */
47enum {
48 /**
49 * Capture pins 31:16 (unbuffered wing) output a test pattern
50 * that can captured on pins 0:15.
51 */
52 PATTERN_EXTERNAL,
53
54 /** Route test pattern internally to capture buffer. */
55 PATTERN_INTERNAL,
56};
57
58static const char *patterns[] = {
59 STR_PATTERN_NONE,
60 STR_PATTERN_EXTERNAL,
61 STR_PATTERN_INTERNAL,
62};
63
64/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a 65SR_PRIV const char *p_ols_channel_names[] = {
4bd80e12 66 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
67 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
68 "24", "25", "26", "27", "28", "29", "30", "31",
4bd80e12 69};
70
71/* Default supported samplerates, can be overridden by device metadata. */
72static const uint64_t samplerates[] = {
73 SR_HZ(10),
74 SR_MHZ(200),
75 SR_HZ(1),
76};
77
78SR_PRIV struct sr_dev_driver p_ols_driver_info;
4bd80e12 79
4f840ce9 80static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
4bd80e12 81{
82 return std_init(sr_ctx, di, LOG_PREFIX);
83}
84
4f840ce9 85static GSList *scan(struct sr_dev_driver *di, GSList *options)
4bd80e12 86{
87 struct sr_dev_inst *sdi;
88 struct drv_context *drvc;
89 struct dev_context *devc;
90 GSList *devices;
91 int ret, i;
92 char buf[70];
93 int bytes_read;
94
95 (void)options;
96
41812aca 97 drvc = di->context;
4bd80e12 98
99 devices = NULL;
100
101 /* Allocate memory for our private device context. */
f57d8ffe 102 devc = g_malloc0(sizeof(struct dev_context));
4bd80e12 103
104 /* Device-specific settings */
b94cff40 105 devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;
4bd80e12 106
107 /* Acquisition settings */
108 devc->limit_samples = devc->capture_ratio = 0;
109 devc->trigger_at = -1;
110 devc->channel_mask = 0xffffffff;
111 devc->flag_reg = 0;
112
113 /* Allocate memory for the incoming ftdi data. */
a95f142e 114 devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE);
4bd80e12 115
116 /* Allocate memory for the FTDI context (ftdic) and initialize it. */
117 if (!(devc->ftdic = ftdi_new())) {
118 sr_err("Failed to initialize libftdi.");
119 goto err_free_ftdi_buf;;
120 }
121
122 /* Try to open the FTDI device */
123 if (p_ols_open(devc) != SR_OK) {
124 goto err_free_ftdic;
125 }
126
127 /* The discovery procedure is like this: first send the Reset
128 * command (0x00) 5 times, since the device could be anywhere
129 * in a 5-byte command. Then send the ID command (0x02).
130 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
131 * have a match.
132 */
133
134 ret = SR_OK;
135 for (i = 0; i < 5; i++) {
136 if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
137 break;
138 }
139 }
140 if (ret != SR_OK) {
141 sr_err("Could not reset device. Quitting.");
142 goto err_close_ftdic;
143 }
144 write_shortcommand(devc, CMD_ID);
145
146 /* Read the response data. */
147 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
148 if (bytes_read < 0) {
149 sr_err("Failed to read FTDI data (%d): %s.",
150 bytes_read, ftdi_get_error_string(devc->ftdic));
151 goto err_close_ftdic;
152 }
153 if (bytes_read == 0) {
154 goto err_close_ftdic;
155 }
156
157 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
158 goto err_close_ftdic;
159
160 /* Definitely using the OLS protocol, check if it supports
161 * the metadata command.
162 */
163 write_shortcommand(devc, CMD_METADATA);
164
165 /* Read the metadata. */
166 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
167 if (bytes_read < 0) {
168 sr_err("Failed to read FTDI data (%d): %s.",
169 bytes_read, ftdi_get_error_string(devc->ftdic));
170 goto err_close_ftdic;
171 }
172 if (bytes_read == 0) {
173 goto err_close_ftdic;
174 }
175
176 /* Close device. We'll reopen it again when we need it. */
177 p_ols_close(devc);
178
179 /* Parse the metadata. */
180 sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);
4bd80e12 181
182 /* Configure samplerate and divider. */
183 if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
184 sr_dbg("Failed to set default samplerate (%"PRIu64").",
185 DEFAULT_SAMPLERATE);
4bd80e12 186
187 drvc->instances = g_slist_append(drvc->instances, sdi);
188 devices = g_slist_append(devices, sdi);
189
190 return devices;
191
192err_close_ftdic:
193 p_ols_close(devc);
194err_free_ftdic:
195 ftdi_free(devc->ftdic); /* NOT free() or g_free()! */
196err_free_ftdi_buf:
197 g_free(devc->ftdi_buf);
4bd80e12 198 g_free(devc);
4bd80e12 199
200 return NULL;
201}
202
4f840ce9 203static GSList *dev_list(const struct sr_dev_driver *di)
4bd80e12 204{
41812aca 205 return ((struct drv_context *)(di->context))->instances;
4bd80e12 206}
207
208static void clear_helper(void *priv)
209{
210 struct dev_context *devc;
211
212 devc = priv;
213
214 ftdi_free(devc->ftdic);
215 g_free(devc->ftdi_buf);
216}
217
4f840ce9 218static int dev_clear(const struct sr_dev_driver *di)
4bd80e12 219{
220 return std_dev_clear(di, clear_helper);
221}
222
4f840ce9 223static int cleanup(const struct sr_dev_driver *di)
4bd80e12 224{
4f840ce9 225 return dev_clear(di);
4bd80e12 226}
227
584560f1 228static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 229 const struct sr_channel_group *cg)
230{
231 struct dev_context *devc;
232
233 (void)cg;
234
235 if (!sdi)
236 return SR_ERR_ARG;
237
238 devc = sdi->priv;
584560f1 239 switch (key) {
4bd80e12 240 case SR_CONF_SAMPLERATE:
241 *data = g_variant_new_uint64(devc->cur_samplerate);
242 break;
243 case SR_CONF_CAPTURE_RATIO:
244 *data = g_variant_new_uint64(devc->capture_ratio);
245 break;
246 case SR_CONF_LIMIT_SAMPLES:
247 *data = g_variant_new_uint64(devc->limit_samples);
248 break;
249 case SR_CONF_PATTERN_MODE:
250 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
251 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
252 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
253 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
254 else
255 *data = g_variant_new_string(STR_PATTERN_NONE);
256 break;
257 case SR_CONF_RLE:
258 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
259 break;
260 case SR_CONF_EXTERNAL_CLOCK:
261 *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
262 break;
263 default:
264 return SR_ERR_NA;
265 }
266
267 return SR_OK;
268}
269
584560f1 270static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
4bd80e12 271 const struct sr_channel_group *cg)
272{
273 struct dev_context *devc;
274 uint16_t flag;
275 uint64_t tmp_u64;
276 int ret;
277 const char *stropt;
278
279 (void)cg;
280
281 if (sdi->status != SR_ST_ACTIVE)
282 return SR_ERR_DEV_CLOSED;
283
284 devc = sdi->priv;
285
584560f1 286 switch (key) {
4bd80e12 287 case SR_CONF_SAMPLERATE:
288 tmp_u64 = g_variant_get_uint64(data);
289 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
290 return SR_ERR_SAMPLERATE;
291 ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
292 break;
293 case SR_CONF_LIMIT_SAMPLES:
294 tmp_u64 = g_variant_get_uint64(data);
295 if (tmp_u64 < MIN_NUM_SAMPLES)
296 return SR_ERR;
297 devc->limit_samples = tmp_u64;
298 ret = SR_OK;
299 break;
300 case SR_CONF_CAPTURE_RATIO:
301 devc->capture_ratio = g_variant_get_uint64(data);
302 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
303 devc->capture_ratio = 0;
304 ret = SR_ERR;
305 } else
306 ret = SR_OK;
307 break;
308 case SR_CONF_EXTERNAL_CLOCK:
309 if (g_variant_get_boolean(data)) {
310 sr_info("Enabling external clock.");
311 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
312 } else {
313 sr_info("Disabled external clock.");
314 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
315 }
316 ret = SR_OK;
317 break;
318 case SR_CONF_PATTERN_MODE:
319 stropt = g_variant_get_string(data, NULL);
320 ret = SR_OK;
321 flag = 0xffff;
322 if (!strcmp(stropt, STR_PATTERN_NONE)) {
323 sr_info("Disabling test modes.");
324 flag = 0x0000;
325 }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
326 sr_info("Enabling internal test mode.");
327 flag = FLAG_INTERNAL_TEST_MODE;
328 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
329 sr_info("Enabling external test mode.");
330 flag = FLAG_EXTERNAL_TEST_MODE;
331 } else {
332 ret = SR_ERR;
333 }
334 if (flag != 0xffff) {
335 devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
336 devc->flag_reg |= flag;
337 }
338 break;
339 case SR_CONF_SWAP:
340 if (g_variant_get_boolean(data)) {
341 sr_info("Enabling channel swapping.");
342 devc->flag_reg |= FLAG_SWAP_CHANNELS;
343 } else {
344 sr_info("Disabling channel swapping.");
345 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
346 }
347 ret = SR_OK;
348 break;
349
350 case SR_CONF_RLE:
351 if (g_variant_get_boolean(data)) {
352 sr_info("Enabling RLE.");
353 devc->flag_reg |= FLAG_RLE;
354 } else {
355 sr_info("Disabling RLE.");
356 devc->flag_reg &= ~FLAG_RLE;
357 }
358 ret = SR_OK;
359 break;
360 default:
361 ret = SR_ERR_NA;
362 }
363
364 return ret;
365}
366
584560f1 367static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 368 const struct sr_channel_group *cg)
369{
370 struct dev_context *devc;
371 GVariant *gvar, *grange[2];
372 GVariantBuilder gvb;
acc885c7 373 int num_pols_changrp, i;
4bd80e12 374
375 (void)cg;
376
377 switch (key) {
378 case SR_CONF_DEVICE_OPTIONS:
584560f1 379 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 380 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
4bd80e12 381 break;
382 case SR_CONF_SAMPLERATE:
383 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
384 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
385 ARRAY_SIZE(samplerates), sizeof(uint64_t));
386 g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
387 *data = g_variant_builder_end(&gvb);
388 break;
acc885c7
BV		 389 case SR_CONF_TRIGGER_MATCH:
390 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
391 trigger_matches, ARRAY_SIZE(trigger_matches),
392 sizeof(int32_t));
4bd80e12 393 break;
394 case SR_CONF_PATTERN_MODE:
395 *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
396 break;
397 case SR_CONF_LIMIT_SAMPLES:
398 if (!sdi)
399 return SR_ERR_ARG;
400 devc = sdi->priv;
401 if (devc->flag_reg & FLAG_RLE)
402 return SR_ERR_NA;
b94cff40 403 if (devc->max_samplebytes == 0)
4bd80e12 404 /* Device didn't specify sample memory size in metadata. */
405 return SR_ERR_NA;
406 /*
407 * Channel groups are turned off if no channels in that group are
408 * enabled, making more room for samples for the enabled group.
409 */
acc885c7
BV		 410 pols_channel_mask(sdi);
411 num_pols_changrp = 0;
4bd80e12 412 for (i = 0; i < 4; i++) {
413 if (devc->channel_mask & (0xff << (i * 8)))
acc885c7 414 num_pols_changrp++;
4bd80e12 415 }
b94cff40 416 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV		 417 if (num_pols_changrp == 3)
418 num_pols_changrp = 4;
4bd80e12 419 grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
acc885c7
BV		 420 if (num_pols_changrp)
421 grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp);
422 else
423 grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
4bd80e12 424 *data = g_variant_new_tuple(grange, 2);
425 break;
426 default:
427 return SR_ERR_NA;
428 }
429
430 return SR_OK;
431}
432
433static int dev_open(struct sr_dev_inst *sdi)
434{
435 struct dev_context *devc;
4bd80e12 436
437 devc = sdi->priv;
438
439 if (p_ols_open(devc) != SR_OK) {
440 return SR_ERR;
441 } else {
dcd438ee 442 sdi->status = SR_ST_ACTIVE;
4bd80e12 443 return SR_OK;
444 }
445}
446
447static int dev_close(struct sr_dev_inst *sdi)
448{
449 int ret;
450 struct dev_context *devc;
451
452 ret = SR_OK;
453 devc = sdi->priv;
454
455 if (sdi->status == SR_ST_ACTIVE) {
456 sr_dbg("Status ACTIVE, closing device.");
457 ret = p_ols_close(devc);
458 } else {
459 sr_spew("Status not ACTIVE, nothing to do.");
460 }
461
462 sdi->status = SR_ST_INACTIVE;
463
464 return ret;
465}
466
4bd80e12 467static int set_trigger(const struct sr_dev_inst *sdi, int stage)
468{
469 struct dev_context *devc;
470 uint8_t cmd, arg[4];
471
472 devc = sdi->priv;
473
474 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
475 arg[0] = devc->trigger_mask[stage] & 0xff;
476 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
477 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
478 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
479 if (write_longcommand(devc, cmd, arg) != SR_OK)
480 return SR_ERR;
481
482 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
483 arg[0] = devc->trigger_value[stage] & 0xff;
484 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
485 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
486 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
487 if (write_longcommand(devc, cmd, arg) != SR_OK)
488 return SR_ERR;
489
490 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
491 arg[0] = arg[1] = arg[3] = 0x00;
492 arg[2] = stage;
493 if (stage == devc->num_stages)
494 /* Last stage, fire when this one matches. */
495 arg[3] |= TRIGGER_START;
496 if (write_longcommand(devc, cmd, arg) != SR_OK)
497 return SR_ERR;
498
1e0de846 499 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
500 arg[0] = devc->trigger_edge[stage] & 0xff;
501 arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
502 arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
503 arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
504 if (write_longcommand(devc, cmd, arg) != SR_OK)
505 return SR_ERR;
506
4bd80e12 507 return SR_OK;
508}
509
84cbaf77
BV		 510static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
511{
512 struct dev_context *devc;
513 uint8_t cmd, arg[4];
514
515 devc = sdi->priv;
516
517 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
518 arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
519 if (write_longcommand(devc, cmd, arg) != SR_OK)
520 return SR_ERR;
521
522 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
523 if (write_longcommand(devc, cmd, arg) != SR_OK)
524 return SR_ERR;
525
526 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
527 arg[2] = 0x03;
528 if (write_longcommand(devc, cmd, arg) != SR_OK)
529 return SR_ERR;
530
531 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
532 arg[2] = 0x00;
533 if (write_longcommand(devc, cmd, arg) != SR_OK)
534 return SR_ERR;
535
536 return SR_OK;
537}
538
4bd80e12 539static int dev_acquisition_start(const struct sr_dev_inst *sdi,
540 void *cb_data)
541{
542 struct dev_context *devc;
543 uint32_t samplecount, readcount, delaycount;
acc885c7 544 uint8_t pols_changrp_mask, arg[4];
b94cff40 545 uint16_t flag_tmp;
acc885c7 546 int num_pols_changrp, samplespercount;
4bd80e12 547 int ret, i;
548
549 if (sdi->status != SR_ST_ACTIVE)
550 return SR_ERR_DEV_CLOSED;
551
552 devc = sdi->priv;
553
acc885c7 554 pols_channel_mask(sdi);
4bd80e12 555
556 /*
557 * Enable/disable channel groups in the flag register according to the
acc885c7
BV		 558 * channel mask. Calculate this here, because num_pols_changrp is
559 * needed to limit readcount.
4bd80e12 560 */
acc885c7
BV		 561 pols_changrp_mask = 0;
562 num_pols_changrp = 0;
4bd80e12 563 for (i = 0; i < 4; i++) {
564 if (devc->channel_mask & (0xff << (i * 8))) {
acc885c7
BV		 565 pols_changrp_mask |= (1 << i);
566 num_pols_changrp++;
4bd80e12 567 }
568 }
b94cff40 569 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV		 570 if (num_pols_changrp == 3)
571 num_pols_changrp = 4;
b94cff40 572 /* maximum number of samples (or RLE counts) the buffer memory can hold */
acc885c7 573 devc->max_samples = devc->max_samplebytes / num_pols_changrp;
4bd80e12 574
575 /*
576 * Limit readcount to prevent reading past the end of the hardware
577 * buffer.
578 */
579 sr_dbg("max_samples = %d", devc->max_samples);
6433156c 580 sr_dbg("limit_samples = %" PRIu64, devc->limit_samples);
b94cff40 581 samplecount = MIN(devc->max_samples, devc->limit_samples);
4bd80e12 582 sr_dbg("Samplecount = %d", samplecount);
583
b94cff40 584 /* In demux mode the OLS is processing two samples per clock */
585 if (devc->flag_reg & FLAG_DEMUX) {
586 samplespercount = 8;
587 }
588 else {
589 samplespercount = 4;
590 }
591
592 readcount = samplecount / samplespercount;
593
4bd80e12 594 /* Rather read too many samples than too few. */
b94cff40 595 if (samplecount % samplespercount != 0)
4bd80e12 596 readcount++;
597
598 /* Basic triggers. */
acc885c7
BV		 599 if (pols_convert_trigger(sdi) != SR_OK) {
600 sr_err("Failed to configure channels.");
601 return SR_ERR;
602 }
84cbaf77 603
acc885c7 604 if (devc->num_stages > 0) {
4bd80e12 605 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
b94cff40 606 devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
84cbaf77
BV		 607 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
608 if (i <= devc->num_stages) {
609 sr_dbg("Setting p-ols stage %d trigger.", i);
610 if ((ret = set_trigger(sdi, i)) != SR_OK)
611 return ret;
612 }
613 else {
614 sr_dbg("Disabling p-ols stage %d trigger.", i);
615 if ((ret = disable_trigger(sdi, i)) != SR_OK)
616 return ret;
617 }
4bd80e12 618 }
619 } else {
620 /* No triggers configured, force trigger on first stage. */
621 sr_dbg("Forcing trigger at stage 0.");
622 if ((ret = set_trigger(sdi, 0)) != SR_OK)
623 return ret;
624 delaycount = readcount;
625 }
626
627 /* Samplerate. */
628 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
629 devc->cur_samplerate, devc->cur_samplerate_divider);
630 arg[0] = devc->cur_samplerate_divider & 0xff;
631 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
632 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
633 arg[3] = 0x00;
634 if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
635 return SR_ERR;
acc885c7 636
4bd80e12 637 /* Send extended sample limit and pre/post-trigger capture ratio. */
638 arg[0] = ((readcount - 1) & 0xff);
639 arg[1] = ((readcount - 1) & 0xff00) >> 8;
640 arg[2] = ((readcount - 1) & 0xff0000) >> 16;
641 arg[3] = ((readcount - 1) & 0xff000000) >> 24;
1e0de846 642 if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
4bd80e12 643 return SR_ERR;
644 arg[0] = ((delaycount - 1) & 0xff);
645 arg[1] = ((delaycount - 1) & 0xff00) >> 8;
646 arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
647 arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
1e0de846 648 if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
4bd80e12 649 return SR_ERR;
acc885c7 650
4bd80e12 651 /* Flag register. */
652 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
653 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
654 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
655 devc->flag_reg & FLAG_RLE ? "on" : "off",
656 devc->flag_reg & FLAG_FILTER ? "on": "off",
657 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
658
b94cff40 659 /*
660 * Enable/disable OLS channel groups in the flag register according
661 * to the channel mask. 1 means "disable channel".
662 */
663 devc->flag_reg &= ~0x3c;
acc885c7 664 devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
b94cff40 665 sr_dbg("flag_reg = %x", devc->flag_reg);
666
667 /*
668 * In demux mode the OLS is processing two 8-bit or 16-bit samples
669 * in parallel and for this to work the lower two bits of the four
670 * "channel_disable" bits must be replicated to the upper two bits.
671 */
672 flag_tmp = devc->flag_reg;
673 if (devc->flag_reg & FLAG_DEMUX) {
674 flag_tmp &= ~0x30;
acc885c7 675 flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
b94cff40 676 }
677 arg[0] = flag_tmp & 0xff;
678 arg[1] = flag_tmp >> 8;
4bd80e12 679 arg[2] = arg[3] = 0x00;
680 if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
681 return SR_ERR;
682
683 /* Start acquisition on the device. */
684 if (write_shortcommand(devc, CMD_RUN) != SR_OK)
685 return SR_ERR;
686
687 /* Reset all operational states. */
688 devc->rle_count = devc->num_transfers = 0;
689 devc->num_samples = devc->num_bytes = 0;
690 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
691 memset(devc->sample, 0, 4);
692
693 /* Send header packet to the session bus. */
694 std_session_send_df_header(cb_data, LOG_PREFIX);
695
696 /* Hook up a dummy handler to receive data from the device. */
c650d3ec 697 sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data,
acc885c7 698 cb_data);
4bd80e12 699
700 return SR_OK;
701}
702
4bd80e12 703static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
704{
705 struct dev_context *devc;
706 struct sr_datafeed_packet packet;
707
708 devc = sdi->priv;
709
710 sr_dbg("Stopping acquisition.");
711 write_shortcommand(devc, CMD_RESET);
712 write_shortcommand(devc, CMD_RESET);
713 write_shortcommand(devc, CMD_RESET);
714 write_shortcommand(devc, CMD_RESET);
715 write_shortcommand(devc, CMD_RESET);
716
dd7a4a71 717 sr_session_source_remove(sdi->session, -1);
4bd80e12 718
719 /* Send end packet to the session bus. */
720 sr_dbg("Sending SR_DF_END.");
721 packet.type = SR_DF_END;
722 sr_session_send(cb_data, &packet);
723
724 return SR_OK;
725}
726
727SR_PRIV struct sr_dev_driver p_ols_driver_info = {
acc885c7 728 .name = "p-ols",
4bd80e12 729 .longname = "Pipistrello OLS",
730 .api_version = 1,
731 .init = init,
732 .cleanup = cleanup,
733 .scan = scan,
734 .dev_list = dev_list,
735 .dev_clear = dev_clear,
736 .config_get = config_get,
737 .config_set = config_set,
738 .config_list = config_list,
739 .dev_open = dev_open,
740 .dev_close = dev_close,
741 .dev_acquisition_start = dev_acquisition_start,
742 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 743 .context = NULL,
4bd80e12 744};
Hardware access and backend lib