]>
Commit | Line | Data |
---|---|---|
f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
f2cd2deb | 31 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
32 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
33 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
8b172e78 KG |
34 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" |
35 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
f2cd2deb | 36 | |
8b172e78 KG |
37 | #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) |
38 | #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) | |
f2cd2deb FS |
39 | #define MAX_SAMPLE_DEPTH 10e9 |
40 | #define MAX_PWM_FREQ SR_MHZ(20) | |
8b172e78 | 41 | #define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */ |
f2cd2deb | 42 | |
00849545 | 43 | /* usb vendor class control requests to the cypress FX2 microcontroller */ |
84fe94bd SA |
44 | #define CMD_FPGA_ENABLE 0x10 |
45 | #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ | |
46 | #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ | |
47 | #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ | |
48 | #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ | |
49 | #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ | |
50 | #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ | |
00849545 | 51 | |
42f6dd55 KG |
52 | /* |
53 | * fpga spi register addresses for control request CMD_FPGA_SPI: | |
54 | * There are around 60 byte-wide registers within the fpga and | |
55 | * these are the base addresses used for accessing them. | |
56 | * On the spi bus, the msb of the address byte is set for read | |
57 | * and cleared for write, but that is handled by the fx2 mcu | |
58 | * as appropriate. In this driver code just use IN transactions | |
59 | * to read, OUT to write. | |
60 | */ | |
84fe94bd SA |
61 | #define REG_RUN 0x00 /* read capture status, write capture start */ |
62 | #define REG_PWM_EN 0x02 /* user pwm channels on/off */ | |
63 | #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ | |
64 | #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ | |
65 | #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ | |
66 | #define REG_TRIGGER 0x20 /* write level and edge trigger config */ | |
67 | #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ | |
68 | #define REG_PWM1 0x70 /* write config for user pwm1 */ | |
69 | #define REG_PWM2 0x78 /* write config for user pwm2 */ | |
f2cd2deb FS |
70 | |
71 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
72 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
73 | void *data, uint16_t wLength) | |
74 | { | |
75 | struct sr_usb_dev_inst *usb; | |
76 | int ret; | |
77 | ||
78 | usb = sdi->conn; | |
79 | ||
80 | if ((ret = libusb_control_transfer( | |
81 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
82 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
83 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
84 | sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", | |
85 | wLength, bRequest, wValue, wIndex, | |
86 | libusb_error_name(ret)); | |
87 | return SR_ERR; | |
88 | } | |
89 | ||
90 | return SR_OK; | |
91 | } | |
92 | ||
93 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
94 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
95 | void *data, uint16_t wLength) | |
96 | { | |
97 | struct sr_usb_dev_inst *usb; | |
98 | int ret; | |
99 | ||
100 | usb = sdi->conn; | |
101 | ||
102 | if ((ret = libusb_control_transfer( | |
103 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
104 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
105 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
106 | sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", | |
107 | wLength, bRequest, wValue, wIndex, | |
108 | libusb_error_name(ret)); | |
109 | return SR_ERR; | |
110 | } | |
111 | ||
112 | return SR_OK; | |
113 | } | |
114 | ||
9de389b1 | 115 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) |
f2cd2deb | 116 | { |
3f48ab02 | 117 | struct dev_context *devc; |
f2cd2deb FS |
118 | struct drv_context *drvc; |
119 | struct sr_usb_dev_inst *usb; | |
120 | struct sr_resource bitstream; | |
c3d40037 HK |
121 | uint8_t buffer[sizeof(uint32_t)]; |
122 | uint8_t *wrptr; | |
f2cd2deb FS |
123 | uint8_t cmd_resp; |
124 | uint8_t block[4096]; | |
3f48ab02 FS |
125 | int len, act_len; |
126 | unsigned int pos; | |
f2cd2deb | 127 | int ret; |
3f48ab02 | 128 | unsigned int zero_pad_to = 0x2c000; |
f2cd2deb | 129 | |
3f48ab02 | 130 | devc = sdi->priv; |
f2cd2deb FS |
131 | drvc = sdi->driver->context; |
132 | usb = sdi->conn; | |
133 | ||
9de389b1 | 134 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 135 | |
9de389b1 | 136 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); |
f2cd2deb | 137 | if (ret != SR_OK) { |
9de389b1 | 138 | sr_err("could not find fpga firmware %s!", bitstream_fname); |
f2cd2deb FS |
139 | return ret; |
140 | } | |
141 | ||
3f48ab02 | 142 | devc->bitstream_size = (uint32_t)bitstream.size; |
c3d40037 HK |
143 | wrptr = buffer; |
144 | write_u32le_inc(&wrptr, devc->bitstream_size); | |
00849545 | 145 | if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { |
f2cd2deb FS |
146 | sr_err("failed to give upload init command"); |
147 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
148 | return ret; | |
149 | } | |
150 | ||
151 | pos = 0; | |
152 | while (1) { | |
3f48ab02 FS |
153 | if (pos < bitstream.size) { |
154 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
155 | if (len < 0) { | |
156 | sr_err("failed to read from fpga bitstream!"); | |
157 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
158 | return SR_ERR; | |
159 | } | |
160 | } else { | |
161 | // fill with zero's until zero_pad_to | |
162 | len = zero_pad_to - pos; | |
163 | if ((unsigned)len > sizeof(block)) | |
164 | len = sizeof(block); | |
165 | memset(&block, 0, len); | |
f2cd2deb FS |
166 | } |
167 | if (len == 0) | |
168 | break; | |
169 | ||
170 | ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
171 | if (ret != 0) { | |
172 | sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); | |
173 | ret = SR_ERR; | |
174 | break; | |
175 | } | |
176 | if (act_len != len) { | |
177 | sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); | |
178 | ret = SR_ERR; | |
179 | break; | |
180 | } | |
181 | pos += len; | |
182 | } | |
183 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
184 | if (ret != 0) | |
185 | return ret; | |
3f48ab02 | 186 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); |
f2cd2deb | 187 | |
00849545 | 188 | if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { |
f2cd2deb FS |
189 | sr_err("failed to read response after FPGA bitstream upload"); |
190 | return ret; | |
191 | } | |
3f48ab02 FS |
192 | if (cmd_resp != 0) { |
193 | sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp); | |
194 | return SR_ERR; | |
195 | } | |
196 | ||
197 | g_usleep(30000); | |
f2cd2deb | 198 | |
00849545 | 199 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
200 | sr_err("failed enable fpga"); |
201 | return ret; | |
202 | } | |
203 | ||
3f48ab02 | 204 | g_usleep(40000); |
f2cd2deb FS |
205 | return SR_OK; |
206 | } | |
207 | ||
208 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
209 | { | |
210 | struct dev_context *devc; | |
f2cd2deb FS |
211 | int ret; |
212 | ||
213 | devc = sdi->priv; | |
f2cd2deb | 214 | |
f2ad79d1 KG |
215 | uint16_t duty_R79,duty_R56; |
216 | uint8_t buf[2 * sizeof(uint16_t)]; | |
217 | uint8_t *wrptr; | |
218 | ||
219 | /* clamp threshold setting within valid range for LA2016 */ | |
220 | if (voltage > 4.0) { | |
221 | voltage = 4.0; | |
222 | } | |
223 | else if (voltage < -4.0) { | |
224 | voltage = -4.0; | |
225 | } | |
226 | ||
227 | /* | |
228 | * The fpga has two programmable pwm outputs which feed a dac that | |
229 | * is used to adjust input offset. The dac changes the input | |
230 | * swing around the fixed fpga input threshold. | |
231 | * The two pwm outputs can be seen on R79 and R56 respectvely. | |
232 | * Frequency is fixed at 100kHz and duty is varied. | |
233 | * The R79 pwm uses just three settings. | |
234 | * The R56 pwm varies with required threshold and its behaviour | |
235 | * also changes depending on the setting of R79 PWM. | |
236 | */ | |
237 | ||
238 | /* | |
239 | * calculate required pwm duty register values from requested threshold voltage | |
240 | * see last page of schematic (on wiki) for an explanation of these numbers | |
241 | */ | |
242 | if (voltage >= 2.9) { | |
243 | duty_R79 = 0; /* this pwm is off (0V)*/ | |
244 | duty_R56 = (uint16_t)(302 * voltage - 363); | |
245 | } | |
246 | else if (voltage <= -0.4) { | |
247 | duty_R79 = 0x02D7; /* 72% duty */ | |
248 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
249 | } | |
250 | else { | |
251 | duty_R79 = 0x00f2; /* 25% duty */ | |
252 | duty_R56 = (uint16_t)(302 * voltage + 121); | |
253 | } | |
254 | ||
255 | /* clamp duty register values at sensible limits */ | |
256 | if (duty_R56 < 10) { | |
257 | duty_R56 = 10; | |
258 | } | |
259 | else if (duty_R56 > 1100) { | |
260 | duty_R56 = 1100; | |
261 | } | |
262 | ||
263 | sr_dbg("set threshold voltage %.2fV", voltage); | |
264 | sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79); | |
265 | ||
266 | wrptr = buf; | |
267 | write_u16le_inc(&wrptr, duty_R56); | |
268 | write_u16le_inc(&wrptr, duty_R79); | |
269 | ||
270 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 271 | if (ret != SR_OK) { |
f2ad79d1 | 272 | sr_err("error setting new threshold voltage of %.2fV", voltage); |
f2cd2deb FS |
273 | return ret; |
274 | } | |
275 | devc->threshold_voltage = voltage; | |
276 | ||
277 | return SR_OK; | |
278 | } | |
279 | ||
280 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
281 | { | |
282 | struct dev_context *devc; | |
283 | uint8_t cfg; | |
284 | int ret; | |
285 | ||
286 | devc = sdi->priv; | |
287 | cfg = 0; | |
288 | ||
289 | if (p1) cfg |= 1 << 0; | |
290 | if (p2) cfg |= 1 << 1; | |
291 | ||
292 | sr_dbg("set pwm enable %d %d", p1, p2); | |
42f6dd55 | 293 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb FS |
294 | if (ret != SR_OK) { |
295 | sr_err("error setting new pwm enable 0x%02x", cfg); | |
296 | return ret; | |
297 | } | |
298 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
299 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
300 | ||
301 | return SR_OK; | |
302 | } | |
303 | ||
304 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) | |
305 | { | |
42f6dd55 | 306 | int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; |
f2cd2deb FS |
307 | struct dev_context *devc; |
308 | pwm_setting_dev_t cfg; | |
309 | pwm_setting_t *setting; | |
310 | int ret; | |
c3d40037 HK |
311 | uint8_t buf[2 * sizeof(uint32_t)]; |
312 | uint8_t *wrptr; | |
f2cd2deb FS |
313 | |
314 | devc = sdi->priv; | |
315 | ||
316 | if (which < 1 || which > 2) { | |
317 | sr_err("invalid pwm channel: %d", which); | |
318 | return SR_ERR; | |
319 | } | |
320 | if (freq > MAX_PWM_FREQ) { | |
321 | sr_err("pwm frequency too high: %.1f", freq); | |
322 | return SR_ERR; | |
323 | } | |
324 | if (duty > 100 || duty < 0) { | |
325 | sr_err("invalid pwm percentage: %f", duty); | |
326 | return SR_ERR; | |
327 | } | |
328 | ||
329 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
330 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
331 | sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); | |
332 | ||
c3d40037 HK |
333 | wrptr = buf; |
334 | write_u32le_inc(&wrptr, cfg.period); | |
335 | write_u32le_inc(&wrptr, cfg.duty); | |
00849545 | 336 | ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); |
f2cd2deb FS |
337 | if (ret != SR_OK) { |
338 | sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); | |
339 | return ret; | |
340 | } | |
341 | setting = &devc->pwm_setting[which - 1]; | |
342 | setting->freq = freq; | |
343 | setting->duty = duty; | |
f2cd2deb FS |
344 | |
345 | return SR_OK; | |
346 | } | |
347 | ||
348 | static int set_defaults(const struct sr_dev_inst *sdi) | |
349 | { | |
350 | struct dev_context *devc; | |
351 | int ret; | |
352 | ||
353 | devc = sdi->priv; | |
354 | ||
355 | devc->capture_ratio = 5; /* percent */ | |
356 | devc->cur_channels = 0xffff; | |
357 | devc->limit_samples = 5000000; | |
8b172e78 | 358 | devc->cur_samplerate = SR_MHZ(100); |
f2cd2deb FS |
359 | |
360 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
361 | if (ret) | |
362 | return ret; | |
363 | ||
364 | ret = enable_pwm(sdi, 0, 0); | |
365 | if (ret) | |
366 | return ret; | |
367 | ||
368 | ret = set_pwm(sdi, 1, 1e3, 50); | |
369 | if (ret) | |
370 | return ret; | |
371 | ||
372 | ret = set_pwm(sdi, 2, 100e3, 50); | |
373 | if (ret) | |
374 | return ret; | |
375 | ||
376 | ret = enable_pwm(sdi, 1, 1); | |
377 | if (ret) | |
378 | return ret; | |
379 | ||
380 | return SR_OK; | |
381 | } | |
382 | ||
383 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
384 | { | |
385 | struct dev_context *devc; | |
386 | struct sr_trigger *trigger; | |
387 | trigger_cfg_t cfg; | |
388 | GSList *stages; | |
389 | GSList *channel; | |
390 | struct sr_trigger_stage *stage1; | |
391 | struct sr_trigger_match *match; | |
392 | uint16_t ch_mask; | |
393 | int ret; | |
c3d40037 HK |
394 | uint8_t buf[4 * sizeof(uint32_t)]; |
395 | uint8_t *wrptr; | |
f2cd2deb FS |
396 | |
397 | devc = sdi->priv; | |
398 | trigger = sr_session_trigger_get(sdi->session); | |
399 | ||
400 | memset(&cfg, 0, sizeof(cfg)); | |
401 | ||
402 | cfg.channels = devc->cur_channels; | |
403 | ||
404 | if (trigger && trigger->stages) { | |
405 | stages = trigger->stages; | |
406 | stage1 = stages->data; | |
407 | if (stages->next) { | |
408 | sr_err("Only one trigger stage supported for now."); | |
409 | return SR_ERR; | |
410 | } | |
411 | channel = stage1->matches; | |
412 | while (channel) { | |
413 | match = channel->data; | |
414 | ch_mask = 1 << match->channel->index; | |
415 | ||
416 | switch (match->match) { | |
417 | case SR_TRIGGER_ZERO: | |
418 | cfg.level |= ch_mask; | |
419 | cfg.high_or_falling &= ~ch_mask; | |
420 | break; | |
421 | case SR_TRIGGER_ONE: | |
422 | cfg.level |= ch_mask; | |
423 | cfg.high_or_falling |= ch_mask; | |
424 | break; | |
425 | case SR_TRIGGER_RISING: | |
426 | if ((cfg.enabled & ~cfg.level)) { | |
427 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
428 | return SR_ERR; | |
429 | } | |
430 | cfg.level &= ~ch_mask; | |
431 | cfg.high_or_falling &= ~ch_mask; | |
432 | break; | |
433 | case SR_TRIGGER_FALLING: | |
434 | if ((cfg.enabled & ~cfg.level)) { | |
435 | sr_err("Only one trigger signal with falling-/rising-edge allowed."); | |
436 | return SR_ERR; | |
437 | } | |
438 | cfg.level &= ~ch_mask; | |
439 | cfg.high_or_falling |= ch_mask; | |
440 | break; | |
441 | default: | |
442 | sr_err("Unknown trigger value."); | |
443 | return SR_ERR; | |
444 | } | |
445 | cfg.enabled |= ch_mask; | |
446 | channel = channel->next; | |
447 | } | |
448 | } | |
449 | sr_dbg("set trigger configuration channels: 0x%04x, " | |
450 | "trigger-enabled 0x%04x, level-triggered 0x%04x, " | |
451 | "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, | |
452 | cfg.high_or_falling); | |
453 | ||
454 | devc->had_triggers_configured = cfg.enabled != 0; | |
455 | ||
c3d40037 HK |
456 | wrptr = buf; |
457 | write_u32le_inc(&wrptr, cfg.channels); | |
458 | write_u32le_inc(&wrptr, cfg.enabled); | |
459 | write_u32le_inc(&wrptr, cfg.level); | |
460 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
42f6dd55 | 461 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb FS |
462 | if (ret != SR_OK) { |
463 | sr_err("error setting trigger config!"); | |
464 | return ret; | |
465 | } | |
466 | ||
467 | return SR_OK; | |
468 | } | |
469 | ||
470 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
471 | { | |
472 | struct dev_context *devc; | |
f2cd2deb | 473 | double clock_divisor; |
f2cd2deb FS |
474 | uint64_t total; |
475 | int ret; | |
c3d40037 HK |
476 | uint16_t divisor; |
477 | uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; | |
478 | uint8_t *wrptr; | |
f2cd2deb FS |
479 | |
480 | devc = sdi->priv; | |
481 | total = 128 * 1024 * 1024; | |
482 | ||
8b172e78 | 483 | if (devc->cur_samplerate > devc->max_samplerate) { |
f2cd2deb FS |
484 | sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); |
485 | return SR_ERR; | |
486 | } | |
487 | ||
8b172e78 | 488 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; |
f2cd2deb FS |
489 | if (clock_divisor > 0xffff) |
490 | clock_divisor = 0xffff; | |
c3d40037 | 491 | divisor = (uint16_t)(clock_divisor + 0.5); |
8b172e78 | 492 | devc->cur_samplerate = devc->max_samplerate / divisor; |
f2cd2deb FS |
493 | |
494 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
495 | sr_err("too high sample depth: %" PRIu64, devc->limit_samples); | |
496 | return SR_ERR; | |
497 | } | |
f2cd2deb FS |
498 | |
499 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
500 | ||
f2cd2deb | 501 | sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", |
955ab604 | 502 | devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio); |
f2cd2deb | 503 | |
c3d40037 HK |
504 | wrptr = buf; |
505 | write_u32le_inc(&wrptr, devc->limit_samples); | |
0d8e1ffc KG |
506 | write_u8_inc(&wrptr, 0); |
507 | write_u32le_inc(&wrptr, devc->pre_trigger_size); | |
84fe94bd | 508 | write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00); |
0d8e1ffc KG |
509 | write_u16le_inc(&wrptr, divisor); |
510 | write_u8_inc(&wrptr, 0); | |
c3d40037 | 511 | |
42f6dd55 | 512 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb FS |
513 | if (ret != SR_OK) { |
514 | sr_err("error setting sample config!"); | |
515 | return ret; | |
516 | } | |
517 | ||
518 | return SR_OK; | |
519 | } | |
520 | ||
7601dca7 KG |
521 | /* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] |
522 | * and the bits are interpreted as follows: | |
523 | * | |
524 | * register 0: | |
525 | * bit0 1= idle | |
526 | * bit1 1= writing to sdram | |
527 | * bit2 0= waiting_for_trigger 1=been_triggered | |
528 | * bit3 0= pretrigger_sampling 1=posttrigger_sampling | |
529 | * ...unknown... | |
530 | * register 1: | |
531 | * meaning of bits unknown (but vendor software reads this, so just do the same) | |
532 | * | |
533 | * The run state values occur in this order: | |
534 | * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) | |
535 | * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) | |
536 | * 0x85EE: running | |
537 | * 0x85ED: idle | |
f2cd2deb FS |
538 | */ |
539 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
540 | { | |
541 | uint16_t state; | |
84fe94bd | 542 | static uint16_t previous_state = 0; |
f2cd2deb FS |
543 | int ret; |
544 | ||
42f6dd55 | 545 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { |
f2cd2deb FS |
546 | sr_err("failed to read run state!"); |
547 | return ret; | |
548 | } | |
7601dca7 KG |
549 | |
550 | /* This function is called about every 50ms. | |
551 | * To avoid filling the log file with redundant information during long captures, | |
552 | * just print a log message if status has changed. | |
553 | */ | |
554 | ||
84fe94bd | 555 | if (state != previous_state) { |
7601dca7 | 556 | previous_state = state; |
84fe94bd | 557 | if ((state & 0x0003) == 0x01) { |
7601dca7 KG |
558 | sr_dbg("run_state: 0x%04x (%s)", state, "idle"); |
559 | } | |
84fe94bd | 560 | else if ((state & 0x000f) == 0x02) { |
7601dca7 KG |
561 | sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling"); |
562 | } | |
84fe94bd | 563 | else if ((state & 0x000f) == 0x0a) { |
7601dca7 KG |
564 | sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger"); |
565 | } | |
84fe94bd | 566 | else if ((state & 0x000f) == 0x0e) { |
7601dca7 KG |
567 | sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling"); |
568 | } | |
569 | else { | |
570 | sr_dbg("run_state: 0x%04x", state); | |
571 | } | |
572 | } | |
f2cd2deb FS |
573 | |
574 | return state; | |
575 | } | |
576 | ||
577 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
578 | { | |
579 | int ret; | |
580 | ||
42f6dd55 | 581 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { |
f2cd2deb FS |
582 | sr_err("failed to send set-run-mode command %d", fast_blinking); |
583 | return ret; | |
584 | } | |
585 | ||
586 | return SR_OK; | |
587 | } | |
588 | ||
589 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
590 | { | |
591 | struct dev_context *devc; | |
592 | int ret; | |
c3d40037 HK |
593 | uint8_t buf[3 * sizeof(uint32_t)]; |
594 | const uint8_t *rdptr; | |
f2cd2deb FS |
595 | |
596 | devc = sdi->priv; | |
597 | ||
42f6dd55 | 598 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { |
f2cd2deb FS |
599 | sr_err("failed to read capture info!"); |
600 | return ret; | |
601 | } | |
c3d40037 HK |
602 | |
603 | rdptr = buf; | |
604 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
605 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
606 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb FS |
607 | |
608 | sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", | |
609 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
610 | devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, | |
611 | devc->info.write_pos, devc->info.write_pos); | |
612 | ||
613 | if (devc->info.n_rep_packets % 5) | |
614 | sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); | |
615 | ||
616 | return SR_OK; | |
617 | } | |
618 | ||
619 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
620 | { | |
621 | char fw_file[1024]; | |
622 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
40a0b2f4 | 623 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
624 | } |
625 | ||
626 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
627 | { | |
628 | struct dev_context *devc; | |
629 | int ret; | |
630 | uint8_t cmd; | |
631 | ||
632 | devc = sdi->priv; | |
633 | ||
634 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
635 | if (ret != SR_OK) | |
636 | return ret; | |
637 | ||
638 | cmd = 0; | |
42f6dd55 | 639 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { |
f2cd2deb FS |
640 | sr_err("failed to send stop sampling command"); |
641 | return ret; | |
642 | } | |
643 | ||
644 | ret = set_trigger_config(sdi); | |
645 | if (ret != SR_OK) | |
646 | return ret; | |
647 | ||
648 | ret = set_sample_config(sdi); | |
649 | if (ret != SR_OK) | |
650 | return ret; | |
651 | ||
652 | return SR_OK; | |
653 | } | |
654 | ||
655 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
656 | { | |
3ebc1cb2 GS |
657 | int ret; |
658 | ||
659 | ret = set_run_mode(sdi, 3); | |
660 | if (ret != SR_OK) | |
661 | return ret; | |
662 | ||
663 | return SR_OK; | |
f2cd2deb FS |
664 | } |
665 | ||
3ebc1cb2 | 666 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 667 | { |
3ebc1cb2 GS |
668 | int ret; |
669 | ||
670 | ret = set_run_mode(sdi, 0); | |
671 | if (ret != SR_OK) | |
672 | return ret; | |
673 | ||
674 | return SR_OK; | |
f2cd2deb FS |
675 | } |
676 | ||
677 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
678 | { | |
3ebc1cb2 GS |
679 | int ret; |
680 | struct dev_context *devc; | |
681 | ||
682 | ret = la2016_stop_acquisition(sdi); | |
683 | if (ret != SR_OK) | |
684 | return ret; | |
685 | ||
686 | devc = sdi ? sdi->priv : NULL; | |
687 | if (devc && devc->transfer) | |
688 | libusb_cancel_transfer(devc->transfer); | |
689 | ||
690 | return SR_OK; | |
f2cd2deb FS |
691 | } |
692 | ||
3ebc1cb2 | 693 | static int la2016_has_triggered(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
694 | { |
695 | uint16_t state; | |
696 | ||
697 | state = run_state(sdi); | |
698 | ||
699 | return (state & 0x3) == 1; | |
700 | } | |
701 | ||
3ebc1cb2 | 702 | static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) |
f2cd2deb FS |
703 | { |
704 | struct dev_context *devc; | |
705 | struct sr_usb_dev_inst *usb; | |
706 | int ret; | |
c3d40037 HK |
707 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
708 | uint8_t *wrptr; | |
f2cd2deb FS |
709 | uint32_t to_read; |
710 | uint8_t *buffer; | |
711 | ||
712 | devc = sdi->priv; | |
713 | usb = sdi->conn; | |
714 | ||
715 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
716 | return ret; | |
717 | ||
c3d40037 HK |
718 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
719 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
720 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
721 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
722 | ||
723 | sr_dbg("want to read %d tfer-packets starting from pos %d", | |
724 | devc->n_transfer_packets_to_read, devc->read_pos); | |
725 | ||
00849545 | 726 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
727 | sr_err("failed to reset bulk state"); |
728 | return ret; | |
729 | } | |
f2cd2deb | 730 | sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); |
c3d40037 HK |
731 | wrptr = wrbuf; |
732 | write_u32le_inc(&wrptr, devc->read_pos); | |
733 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
42f6dd55 | 734 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { |
f2cd2deb FS |
735 | sr_err("failed to send bulk config"); |
736 | return ret; | |
737 | } | |
00849545 | 738 | if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
739 | sr_err("failed to unblock bulk transfers"); |
740 | return ret; | |
741 | } | |
742 | ||
743 | to_read = devc->n_bytes_to_read; | |
e847645b KG |
744 | /* choose a buffer size for all of the usb transfers */ |
745 | if (to_read >= LA2016_USB_BUFSZ) | |
746 | to_read = LA2016_USB_BUFSZ; /* multiple transfers */ | |
747 | else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */ | |
748 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); | |
f2cd2deb FS |
749 | buffer = g_try_malloc(to_read); |
750 | if (!buffer) { | |
751 | sr_err("Failed to allocate %d bytes for bulk transfer", to_read); | |
752 | return SR_ERR_MALLOC; | |
753 | } | |
754 | ||
755 | devc->transfer = libusb_alloc_transfer(0); | |
756 | libusb_fill_bulk_transfer( | |
757 | devc->transfer, usb->devhdl, | |
758 | 0x86, buffer, to_read, | |
759 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
760 | ||
761 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
762 | sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); | |
763 | libusb_free_transfer(devc->transfer); | |
764 | devc->transfer = NULL; | |
765 | g_free(buffer); | |
766 | return SR_ERR; | |
767 | } | |
768 | ||
769 | return SR_OK; | |
770 | } | |
771 | ||
dfac9592 GS |
772 | static void send_chunk(struct sr_dev_inst *sdi, |
773 | const uint8_t *packets, unsigned int num_tfers) | |
774 | { | |
775 | struct dev_context *devc; | |
776 | struct sr_datafeed_logic logic; | |
777 | struct sr_datafeed_packet sr_packet; | |
778 | unsigned int max_samples, n_samples, total_samples, free_n_samples; | |
779 | unsigned int i, j, k; | |
780 | int do_signal_trigger; | |
781 | uint16_t *wp; | |
782 | const uint8_t *rp; | |
783 | uint16_t state; | |
784 | uint8_t repetitions; | |
785 | ||
786 | devc = sdi->priv; | |
787 | ||
788 | logic.unitsize = 2; | |
789 | logic.data = devc->convbuffer; | |
790 | ||
791 | sr_packet.type = SR_DF_LOGIC; | |
792 | sr_packet.payload = &logic; | |
793 | ||
794 | max_samples = devc->convbuffer_size / 2; | |
795 | n_samples = 0; | |
796 | wp = (uint16_t *)devc->convbuffer; | |
797 | total_samples = 0; | |
798 | do_signal_trigger = 0; | |
799 | ||
800 | if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { | |
801 | std_session_send_df_trigger(sdi); | |
802 | devc->reading_behind_trigger = 1; | |
803 | } | |
804 | ||
805 | rp = packets; | |
806 | for (i = 0; i < num_tfers; i++) { | |
807 | for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { | |
808 | free_n_samples = max_samples - n_samples; | |
809 | if (free_n_samples < 256 || do_signal_trigger) { | |
810 | logic.length = n_samples * 2; | |
811 | sr_session_send(sdi, &sr_packet); | |
812 | n_samples = 0; | |
813 | wp = (uint16_t *)devc->convbuffer; | |
814 | if (do_signal_trigger) { | |
815 | std_session_send_df_trigger(sdi); | |
816 | do_signal_trigger = 0; | |
817 | } | |
818 | } | |
819 | ||
820 | state = read_u16le_inc(&rp); | |
821 | repetitions = read_u8_inc(&rp); | |
822 | for (j = 0; j < repetitions; j++) | |
823 | *wp++ = state; | |
824 | ||
825 | n_samples += repetitions; | |
826 | total_samples += repetitions; | |
827 | devc->total_samples += repetitions; | |
828 | if (!devc->reading_behind_trigger) { | |
829 | devc->n_reps_until_trigger--; | |
830 | if (devc->n_reps_until_trigger == 0) { | |
831 | devc->reading_behind_trigger = 1; | |
832 | do_signal_trigger = 1; | |
833 | sr_dbg(" here is trigger position after %" PRIu64 " samples, %.6fms", | |
834 | devc->total_samples, | |
835 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
836 | } | |
837 | } | |
838 | } | |
839 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
840 | } | |
841 | if (n_samples) { | |
842 | logic.length = n_samples * 2; | |
843 | sr_session_send(sdi, &sr_packet); | |
844 | if (do_signal_trigger) { | |
845 | std_session_send_df_trigger(sdi); | |
846 | } | |
847 | } | |
848 | sr_dbg("send_chunk done after %d samples", total_samples); | |
849 | } | |
850 | ||
851 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
852 | { | |
853 | struct sr_dev_inst *sdi; | |
854 | struct dev_context *devc; | |
855 | struct sr_usb_dev_inst *usb; | |
856 | int ret; | |
857 | ||
858 | sdi = transfer->user_data; | |
859 | devc = sdi->priv; | |
860 | usb = sdi->conn; | |
861 | ||
862 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
863 | libusb_error_name(transfer->status), transfer->actual_length); | |
864 | ||
865 | if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { | |
866 | sr_err("bulk transfer timeout!"); | |
867 | devc->transfer_finished = 1; | |
868 | } | |
869 | send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); | |
870 | ||
871 | devc->n_bytes_to_read -= transfer->actual_length; | |
872 | if (devc->n_bytes_to_read) { | |
873 | uint32_t to_read = devc->n_bytes_to_read; | |
874 | /* determine read size for the next usb transfer */ | |
875 | if (to_read >= LA2016_USB_BUFSZ) | |
876 | to_read = LA2016_USB_BUFSZ; | |
877 | else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */ | |
878 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); | |
879 | libusb_fill_bulk_transfer( | |
880 | transfer, usb->devhdl, | |
881 | 0x86, transfer->buffer, to_read, | |
882 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
883 | ||
884 | if ((ret = libusb_submit_transfer(transfer)) == 0) | |
885 | return; | |
886 | sr_err("Failed to submit further transfer: %s.", libusb_error_name(ret)); | |
887 | } | |
888 | ||
889 | g_free(transfer->buffer); | |
890 | libusb_free_transfer(transfer); | |
891 | devc->transfer_finished = 1; | |
892 | } | |
893 | ||
894 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
895 | { | |
896 | const struct sr_dev_inst *sdi; | |
897 | struct dev_context *devc; | |
898 | struct drv_context *drvc; | |
899 | struct timeval tv; | |
900 | ||
901 | (void)fd; | |
902 | (void)revents; | |
903 | ||
904 | sdi = cb_data; | |
905 | devc = sdi->priv; | |
906 | drvc = sdi->driver->context; | |
907 | ||
908 | if (devc->have_trigger == 0) { | |
909 | if (la2016_has_triggered(sdi) == 0) { | |
910 | /* not yet ready for download */ | |
911 | return TRUE; | |
912 | } | |
913 | devc->have_trigger = 1; | |
914 | devc->transfer_finished = 0; | |
915 | devc->reading_behind_trigger = 0; | |
916 | devc->total_samples = 0; | |
917 | /* we can start retrieving data! */ | |
918 | if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { | |
919 | sr_err("failed to start retrieval!"); | |
920 | return FALSE; | |
921 | } | |
922 | sr_dbg("retrieval is started..."); | |
923 | std_session_send_df_frame_begin(sdi); | |
924 | ||
925 | return TRUE; | |
926 | } | |
927 | ||
928 | tv.tv_sec = tv.tv_usec = 0; | |
929 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
930 | ||
931 | if (devc->transfer_finished) { | |
932 | sr_dbg("transfer is finished!"); | |
933 | std_session_send_df_frame_end(sdi); | |
934 | ||
935 | usb_source_remove(sdi->session, drvc->sr_ctx); | |
936 | std_session_send_df_end(sdi); | |
937 | ||
938 | la2016_stop_acquisition(sdi); | |
939 | ||
940 | g_free(devc->convbuffer); | |
941 | devc->convbuffer = NULL; | |
942 | ||
943 | devc->transfer = NULL; | |
944 | ||
945 | sr_dbg("transfer is now finished"); | |
946 | } | |
947 | ||
948 | return TRUE; | |
949 | } | |
950 | ||
f2cd2deb FS |
951 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) |
952 | { | |
8b172e78 | 953 | struct dev_context *devc; |
f2cd2deb | 954 | uint16_t state; |
9de389b1 KG |
955 | uint8_t buf[8]; |
956 | int16_t purchase_date_bcd[2]; | |
957 | uint8_t magic; | |
958 | int ret; | |
f2cd2deb | 959 | |
8b172e78 KG |
960 | devc = sdi->priv; |
961 | ||
9de389b1 KG |
962 | /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit |
963 | * complemented checksum; e.g. 2004DFFB = 2020-April. | |
964 | * This helps to identify the age of devices if unknown magic numbers occur. | |
965 | */ | |
966 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { | |
967 | sr_err("failed to read eeprom purchase_date_bcd"); | |
968 | } | |
969 | else { | |
970 | sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff); | |
84fe94bd | 971 | if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { |
9de389b1 KG |
972 | sr_err("purchase date: checksum failure"); |
973 | } | |
f2cd2deb | 974 | } |
f2cd2deb | 975 | |
9de389b1 KG |
976 | /* |
977 | * There are four known kingst logic analyser devices which use this same usb vid and pid: | |
978 | * LA2016, LA1016 and the older revision of each of these. They all use the same hardware | |
979 | * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are | |
980 | * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. | |
981 | * For example; | |
982 | * | |
983 | * magic=0x08 | |
984 | * | ~magic=0xf7 | |
985 | * | | | |
986 | * 08F7000008F710EF | |
987 | * | | | |
988 | * | ~magic-backup | |
989 | * magic-backup | |
990 | * | |
991 | * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. | |
992 | * Changing the magic byte on newer device to older magic causes OEM software to load | |
993 | * the older fpga bitstream. The device then functions but has channels out of order. | |
994 | * It's likely the bitstreams were changed to move input channel pins due to PCB changes. | |
995 | * | |
996 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
997 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
998 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
999 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" | |
1000 | * | |
1001 | * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing | |
1002 | * the vendor software actions, either raising errors or loading specific bitstreams. | |
1003 | * | |
1004 | * Note: | |
1005 | * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream | |
1006 | * will not authenticate with ic U10, which has different security coding for each device type. | |
1007 | */ | |
1008 | ||
1009 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { | |
1010 | sr_err("failed to read eeprom device identifier bytes"); | |
f2cd2deb FS |
1011 | return ret; |
1012 | } | |
f2cd2deb | 1013 | |
9de389b1 KG |
1014 | magic = 0; |
1015 | if (buf[0] == (0x0ff & ~buf[1])) { | |
1016 | /* primary copy of magic passes complement check */ | |
1017 | magic = buf[0]; | |
1018 | } | |
1019 | else if (buf[4] == (0x0ff & ~buf[5])) { | |
1020 | /* backup copy of magic passes complement check */ | |
1021 | sr_dbg("device_type: using backup copy of magic number"); | |
1022 | magic = buf[4]; | |
f2cd2deb FS |
1023 | } |
1024 | ||
9de389b1 KG |
1025 | sr_dbg("device_type: magic number is %hhu", magic); |
1026 | ||
1027 | /* select the correct fpga bitstream for this device */ | |
1028 | switch (magic) { | |
1029 | case 2: | |
1030 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); | |
8b172e78 KG |
1031 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1032 | break; | |
1033 | case 3: | |
1034 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); | |
1035 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
9de389b1 KG |
1036 | break; |
1037 | case 8: | |
1038 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); | |
8b172e78 KG |
1039 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1040 | break; | |
1041 | case 9: | |
1042 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); | |
1043 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
9de389b1 KG |
1044 | break; |
1045 | default: | |
8b172e78 | 1046 | sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016"); |
3f48ab02 FS |
1047 | return SR_ERR; |
1048 | } | |
f2cd2deb | 1049 | |
9de389b1 KG |
1050 | if (ret != SR_OK) { |
1051 | sr_err("failed to upload fpga bitstream"); | |
1052 | return ret; | |
1053 | } | |
1054 | ||
f2cd2deb | 1055 | state = run_state(sdi); |
9de389b1 | 1056 | if (state != 0x85e9) { |
f2cd2deb | 1057 | sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); |
9de389b1 | 1058 | } |
f2cd2deb | 1059 | |
00849545 | 1060 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
bb706a76 | 1061 | sr_err("failed to send CMD_BULK_RESET"); |
f2cd2deb FS |
1062 | return ret; |
1063 | } | |
9de389b1 | 1064 | |
f2cd2deb FS |
1065 | sr_dbg("device should be initialized"); |
1066 | ||
1067 | return set_defaults(sdi); | |
1068 | } | |
1069 | ||
1070 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
1071 | { | |
1072 | int ret; | |
1073 | ||
00849545 | 1074 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
f2cd2deb FS |
1075 | sr_err("failed to send deinit command"); |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | return SR_OK; | |
1080 | } |