[libsigrok.git] / src / hardware / ikalogic-scanaplus / protocol.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <config.h>
#include "protocol.h"

/*
 * Logic level thresholds.
 *
 * For each of the two channel groups (1-4 and 5-9), the logic level
 * threshold can be set independently.
 *
 * The threshold can be set to values that are usable for systems with
 * different voltage levels, e.g. for 1.8V or 3.3V systems.
 *
 * The actual threshold value is always the middle of the values below.
 * E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
 * means that values <= 0.9V are considered to be a logic 0/low, and
 * values > 0.9V are considered to be a logic 1/high.
 *
 *  - 1.2V system: threshold = 0.6V
 *  - 1.5V system: threshold = 0.75V
 *  - 1.8V system: threshold = 0.9V
 *  - 2.8V system: threshold = 1.4V
 *  - 3.3V system: threshold = 1.65V
 */
#define THRESHOLD_1_2V_SYSTEM 0x2e
#define THRESHOLD_1_5V_SYSTEM 0x39
#define THRESHOLD_1_8V_SYSTEM 0x45
#define THRESHOLD_2_8V_SYSTEM 0x6c
#define THRESHOLD_3_3V_SYSTEM 0x7f

static int scanaplus_write(struct dev_context *devc, uint8_t *buf, int size)
{
	int i, bytes_written;
	GString *s;

	/* Note: Caller checks devc, devc->ftdic, buf, size. */

	s = g_string_sized_new(100);
	g_string_printf(s, "Writing %d bytes: ", size);
	for (i = 0; i < size; i++)
		g_string_append_printf(s, "0x%02x ", buf[i]);
	sr_spew("%s", s->str);
	g_string_free(s, TRUE);

	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	if (bytes_written < 0) {
		sr_err("Failed to write FTDI data (%d): %s.",
		       bytes_written, ftdi_get_error_string(devc->ftdic));
	} else if (bytes_written != size) {
		sr_err("FTDI write error, only %d/%d bytes written: %s.",
		       bytes_written, size, ftdi_get_error_string(devc->ftdic));
	}

	return bytes_written;
}

SR_PRIV int scanaplus_close(struct dev_context *devc)
{
	int ret;

	/* Note: Caller checks devc and devc->ftdic. */

	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
		sr_err("Failed to close FTDI device (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	return SR_OK;
}

static void scanaplus_uncompress_block(struct dev_context *devc,
				       uint64_t num_bytes)
{
	uint64_t i, j;
	uint8_t num_samples, low, high;

	for (i = 0; i < num_bytes; i += 2) {
		num_samples = devc->compressed_buf[i + 0] >> 1;

		low = devc->compressed_buf[i + 0] & (1 << 0);
		high = devc->compressed_buf[i + 1];

		for (j = 0; j < num_samples; j++) {
			devc->sample_buf[devc->bytes_received++] = high;
			devc->sample_buf[devc->bytes_received++] = low;
		}
	}
}

static void send_samples(struct dev_context *devc, uint64_t samples_to_send)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;

	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = samples_to_send * 2;
	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
	logic.data = devc->sample_buf;
	sr_session_send(devc->cb_data, &packet);

	devc->samples_sent += samples_to_send;
	devc->bytes_received -= samples_to_send * 2;
}

SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
{
	int ret;
	uint16_t val1, val2;

	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
		sr_err("Failed to read EEPROM index 16 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
		sr_err("Failed to read EEPROM index 17 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	/*
	 * Note: Bit 7 of the three bytes must not be used, apparently.
	 *
	 * Even though the three bits can be either 0 or 1 (we've seen both
	 * in actual ScanaPLUS devices), the device ID as sent to the FPGA
	 * has bit 7 of each byte zero'd out.
	 *
	 * It is unknown whether bit 7 of these bytes has any meaning,
	 * whether it's used somewhere, or whether it can be simply ignored.
	 */
	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);

	return SR_OK;
}

static int scanaplus_clear_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

static int scanaplus_send_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = devc->devid[0];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = devc->devid[1];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = devc->devid[2];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_init(struct dev_context *devc)
{
	int i;
	uint8_t buf[8];

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x89;
	buf[1] = 0x64;
	buf[2] = 0x8a;
	buf[3] = 0x64;
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8d;
	buf[1] = 0x01;
	buf[2] = 0x8d;
	buf[3] = 0x05;
	buf[4] = 0x8d;
	buf[5] = 0x01;
	buf[6] = 0x8d;
	buf[7] = 0x02;
	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
		return SR_ERR;

	for (i = 0; i < 57; i++) {
		buf[0] = 0x8d;
		buf[1] = 0x06;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;

		buf[0] = 0x8d;
		buf[1] = 0x02;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;
	}

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
{
	uint8_t buf[4];

	/* Threshold and differential channel settings not yet implemented. */

	buf[0] = 0x89;
	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
	buf[2] = 0x8a;
	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	if (scanaplus_clear_device_id(devc) < 0)
		return SR_ERR;

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
{
	int bytes_read;
	struct sr_dev_inst *sdi;
	struct dev_context *devc;
	uint64_t max, n;

	(void)fd;
	(void)revents;

	if (!(sdi = cb_data))
		return TRUE;

	if (!(devc = sdi->priv))
		return TRUE;

	if (!devc->ftdic)
		return TRUE;

	/* Get a block of data. */
	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
				    COMPRESSED_BUF_SIZE);
	if (bytes_read < 0) {
		sr_err("Failed to read FTDI data (%d): %s.",
		       bytes_read, ftdi_get_error_string(devc->ftdic));
		sdi->driver->dev_acquisition_stop(sdi, sdi);
		return FALSE;
	}
	if (bytes_read == 0) {
		sr_spew("Received 0 bytes, nothing to do.");
		return TRUE;
	}

	/*
	 * After a ScanaPLUS acquisition starts, a bunch of samples will be
	 * returned as all-zero, no matter which signals are actually present
	 * on the channels. This is probably due to the FPGA reconfiguring some
	 * of its internal state/config during this time.
	 *
	 * As far as we know there is apparently no way for the PC-side to
	 * know when this "reconfiguration" starts or ends. The FTDI chip
	 * will return all-zero "dummy" samples during this time, which is
	 * indistinguishable from actual all-zero samples.
	 *
	 * We currently simply ignore the first 64kB of data after an
	 * acquisition starts. Empirical tests have shown that the
	 * "reconfigure" time is a lot less than that usually.
	 */
	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
		/* Ignore the first 64kB of data of every acquisition. */
		sr_spew("Ignoring first 64kB chunk of data.");
		devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
		return TRUE;
	}

	/* TODO: Handle bytes_read which is not a multiple of 2? */
	scanaplus_uncompress_block(devc, bytes_read);

	n = devc->samples_sent + (devc->bytes_received / 2);
	max = (SR_MHZ(100) / 1000) * devc->limit_msec;

	if (devc->limit_samples && (n >= devc->limit_samples)) {
		send_samples(devc, devc->limit_samples - devc->samples_sent);
		sr_info("Requested number of samples reached.");
		sdi->driver->dev_acquisition_stop(sdi, cb_data);
		return TRUE;
	} else if (devc->limit_msec && (n >= max)) {
		send_samples(devc, max - devc->samples_sent);
		sr_info("Requested time limit reached.");
		sdi->driver->dev_acquisition_stop(sdi, cb_data);
		return TRUE;
	} else {
		send_samples(devc, devc->bytes_received / 2);
	}

	return TRUE;
}
Commit	Line	Data
fdf4a1f5 UH	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
6ec6c43b	21	#include <config.h>
fdf4a1f5 UH	22	#include "protocol.h"
fdf4a1f5 UH	23
ab4bb6eb UH	24	/*
	25	* Logic level thresholds.
	26	*
	27	* For each of the two channel groups (1-4 and 5-9), the logic level
	28	* threshold can be set independently.
	29	*
	30	* The threshold can be set to values that are usable for systems with
	31	* different voltage levels, e.g. for 1.8V or 3.3V systems.
	32	*
	33	* The actual threshold value is always the middle of the values below.
	34	* E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
	35	* means that values <= 0.9V are considered to be a logic 0/low, and
	36	* values > 0.9V are considered to be a logic 1/high.
	37	*
	38	* - 1.2V system: threshold = 0.6V
	39	* - 1.5V system: threshold = 0.75V
	40	* - 1.8V system: threshold = 0.9V
	41	* - 2.8V system: threshold = 1.4V
	42	* - 3.3V system: threshold = 1.65V
	43	*/
	44	#define THRESHOLD_1_2V_SYSTEM 0x2e
	45	#define THRESHOLD_1_5V_SYSTEM 0x39
	46	#define THRESHOLD_1_8V_SYSTEM 0x45
	47	#define THRESHOLD_2_8V_SYSTEM 0x6c
	48	#define THRESHOLD_3_3V_SYSTEM 0x7f
	49
	50	static int scanaplus_write(struct dev_context devc, uint8_t buf, int size)
	51	{
	52	int i, bytes_written;
	53	GString *s;
	54
	55	/* Note: Caller checks devc, devc->ftdic, buf, size. */
	56
	57	s = g_string_sized_new(100);
	58	g_string_printf(s, "Writing %d bytes: ", size);
	59	for (i = 0; i < size; i++)
	60	g_string_append_printf(s, "0x%02x ", buf[i]);
	61	sr_spew("%s", s->str);
	62	g_string_free(s, TRUE);
	63
	64	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	65	if (bytes_written < 0) {
	66	sr_err("Failed to write FTDI data (%d): %s.",
	67	bytes_written, ftdi_get_error_string(devc->ftdic));
	68	} else if (bytes_written != size) {
	69	sr_err("FTDI write error, only %d/%d bytes written: %s.",
	70	bytes_written, size, ftdi_get_error_string(devc->ftdic));
	71	}
	72
	73	return bytes_written;
	74	}
	75
	76	SR_PRIV int scanaplus_close(struct dev_context *devc)
	77	{
	78	int ret;
	79
	80	/* Note: Caller checks devc and devc->ftdic. */
	81
	82	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
	83	sr_err("Failed to close FTDI device (%d): %s.",
	84	ret, ftdi_get_error_string(devc->ftdic));
	85	return SR_ERR;
	86	}
	87
88	return SR_OK;
89	}
90
91	static void scanaplus_uncompress_block(struct dev_context *devc,
92	uint64_t num_bytes)
fdf4a1f5	93	{
ab4bb6eb UH	94	uint64_t i, j;
	95	uint8_t num_samples, low, high;
	96
	97	for (i = 0; i < num_bytes; i += 2) {
	98	num_samples = devc->compressed_buf[i + 0] >> 1;
	99
	100	low = devc->compressed_buf[i + 0] & (1 << 0);
	101	high = devc->compressed_buf[i + 1];
	102
	103	for (j = 0; j < num_samples; j++) {
	104	devc->sample_buf[devc->bytes_received++] = high;
	105	devc->sample_buf[devc->bytes_received++] = low;
	106	}
	107	}
	108	}
	109
	110	static void send_samples(struct dev_context *devc, uint64_t samples_to_send)
	111	{
	112	struct sr_datafeed_packet packet;
	113	struct sr_datafeed_logic logic;
	114
	115	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);
	116
	117	packet.type = SR_DF_LOGIC;
	118	packet.payload = &logic;
	119	logic.length = samples_to_send * 2;
ba7dd8bb	120	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
ab4bb6eb UH	121	logic.data = devc->sample_buf;
	122	sr_session_send(devc->cb_data, &packet);
	123
	124	devc->samples_sent += samples_to_send;
	125	devc->bytes_received -= samples_to_send * 2;
	126	}
	127
	128	SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
	129	{
	130	int ret;
	131	uint16_t val1, val2;
	132
	133	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	134	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
	135	sr_err("Failed to read EEPROM index 16 (%d): %s.",
	136	ret, ftdi_get_error_string(devc->ftdic));
	137	return SR_ERR;
	138	}
	139	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
	140	sr_err("Failed to read EEPROM index 17 (%d): %s.",
	141	ret, ftdi_get_error_string(devc->ftdic));
	142	return SR_ERR;
	143	}
	144
	145	/*
	146	* Note: Bit 7 of the three bytes must not be used, apparently.
	147	*
	148	* Even though the three bits can be either 0 or 1 (we've seen both
	149	* in actual ScanaPLUS devices), the device ID as sent to the FPGA
	150	* has bit 7 of each byte zero'd out.
	151	*
	152	* It is unknown whether bit 7 of these bytes has any meaning,
	153	* whether it's used somewhere, or whether it can be simply ignored.
	154	*/
	155	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	156	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	157	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);
	158
	159	return SR_OK;
	160	}
	161
	162	static int scanaplus_clear_device_id(struct dev_context *devc)
	163	{
	164	uint8_t buf[2];
	165
	166	buf[0] = 0x8c;
	167	buf[1] = 0x00;
	168	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	169	return SR_ERR;
	170
	171	buf[0] = 0x8e;
	172	buf[1] = 0x00;
	173	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	174	return SR_ERR;
	175
	176	buf[0] = 0x8f;
	177	buf[1] = 0x00;
	178	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	179	return SR_ERR;
	180
	181	return SR_OK;
	182	}
	183
	184	static int scanaplus_send_device_id(struct dev_context *devc)
185	{
186	uint8_t buf[2];
187
188	buf[0] = 0x8c;
189	buf[1] = devc->devid[0];
190	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
191	return SR_ERR;
192
193	buf[0] = 0x8e;
194	buf[1] = devc->devid[1];
195	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
196	return SR_ERR;
197
198	buf[0] = 0x8f;
199	buf[1] = devc->devid[2];
200	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
201	return SR_ERR;
202
203	return SR_OK;
204	}
205
206	SR_PRIV int scanaplus_init(struct dev_context *devc)
207	{
208	int i;
209	uint8_t buf[8];
210
211	buf[0] = 0x88;
212	buf[1] = 0x41;
213	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
214	return SR_ERR;
215
216	buf[0] = 0x89;
217	buf[1] = 0x64;
218	buf[2] = 0x8a;
219	buf[3] = 0x64;
220	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
221	return SR_ERR;
222
223	buf[0] = 0x88;
224	buf[1] = 0x41;
225	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
226	return SR_ERR;
227
228	buf[0] = 0x88;
229	buf[1] = 0x40;
230	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
231	return SR_ERR;
232
233	buf[0] = 0x8d;
234	buf[1] = 0x01;
235	buf[2] = 0x8d;
236	buf[3] = 0x05;
237	buf[4] = 0x8d;
238	buf[5] = 0x01;
239	buf[6] = 0x8d;
240	buf[7] = 0x02;
241	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
242	return SR_ERR;
243
244	for (i = 0; i < 57; i++) {
245	buf[0] = 0x8d;
246	buf[1] = 0x06;
247	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
248	return SR_ERR;
249
250	buf[0] = 0x8d;
251	buf[1] = 0x02;
252	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
253	return SR_ERR;
254	}
255
256	if (scanaplus_send_device_id(devc) < 0)
257	return SR_ERR;
258
259	buf[0] = 0x88;
260	buf[1] = 0x40;
261	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
262	return SR_ERR;
263
264	return SR_OK;
265	}
266
267	SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
268	{
269	uint8_t buf[4];
270
ba7dd8bb	271	/* Threshold and differential channel settings not yet implemented. */
ab4bb6eb UH	272
ab4bb6eb UH	273	buf[0] = 0x89;
ba7dd8bb	274	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
ab4bb6eb	275	buf[2] = 0x8a;
ba7dd8bb	276	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
ab4bb6eb UH	277	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
	278	return SR_ERR;
	279
	280	buf[0] = 0x88;
ba7dd8bb	281	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
ab4bb6eb UH	282	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	283	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	284	return SR_ERR;
	285
	286	if (scanaplus_clear_device_id(devc) < 0)
	287	return SR_ERR;
	288
	289	if (scanaplus_send_device_id(devc) < 0)
	290	return SR_ERR;
	291
	292	return SR_OK;
	293	}
	294
	295	SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
	296	{
	297	int bytes_read;
	298	struct sr_dev_inst *sdi;
fdf4a1f5	299	struct dev_context *devc;
ab4bb6eb	300	uint64_t max, n;
fdf4a1f5 UH	301
fdf4a1f5 UH	302	(void)fd;
ab4bb6eb	303	(void)revents;
fdf4a1f5 UH	304
	305	if (!(sdi = cb_data))
	306	return TRUE;
	307
	308	if (!(devc = sdi->priv))
	309	return TRUE;
	310
ab4bb6eb UH	311	if (!devc->ftdic)
	312	return TRUE;
	313
	314	/* Get a block of data. */
	315	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
	316	COMPRESSED_BUF_SIZE);
	317	if (bytes_read < 0) {
	318	sr_err("Failed to read FTDI data (%d): %s.",
	319	bytes_read, ftdi_get_error_string(devc->ftdic));
	320	sdi->driver->dev_acquisition_stop(sdi, sdi);
	321	return FALSE;
	322	}
	323	if (bytes_read == 0) {
	324	sr_spew("Received 0 bytes, nothing to do.");
	325	return TRUE;
	326	}
	327
	328	/*
	329	* After a ScanaPLUS acquisition starts, a bunch of samples will be
	330	* returned as all-zero, no matter which signals are actually present
ba7dd8bb	331	* on the channels. This is probably due to the FPGA reconfiguring some
ab4bb6eb UH	332	* of its internal state/config during this time.
	333	*
	334	* As far as we know there is apparently no way for the PC-side to
	335	* know when this "reconfiguration" starts or ends. The FTDI chip
	336	* will return all-zero "dummy" samples during this time, which is
	337	* indistinguishable from actual all-zero samples.
	338	*
	339	* We currently simply ignore the first 64kB of data after an
	340	* acquisition starts. Empirical tests have shown that the
	341	* "reconfigure" time is a lot less than that usually.
	342	*/
	343	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
	344	/* Ignore the first 64kB of data of every acquisition. */
	345	sr_spew("Ignoring first 64kB chunk of data.");
	346	devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
	347	return TRUE;
	348	}
	349
	350	/* TODO: Handle bytes_read which is not a multiple of 2? */
	351	scanaplus_uncompress_block(devc, bytes_read);
	352
	353	n = devc->samples_sent + (devc->bytes_received / 2);
	354	max = (SR_MHZ(100) / 1000) * devc->limit_msec;
	355
	356	if (devc->limit_samples && (n >= devc->limit_samples)) {
	357	send_samples(devc, devc->limit_samples - devc->samples_sent);
	358	sr_info("Requested number of samples reached.");
	359	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	360	return TRUE;
	361	} else if (devc->limit_msec && (n >= max)) {
	362	send_samples(devc, max - devc->samples_sent);
	363	sr_info("Requested time limit reached.");
	364	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	365	return TRUE;
	366	} else {
	367	send_samples(devc, devc->bytes_received / 2);
fdf4a1f5 UH	368	}
	369
	370	return TRUE;
	371	}