[libsigrok.git] / src / hardware / ikalogic-scanaplus / protocol.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

/*
 * Logic level thresholds.
 *
 * For each of the two channel groups (1-4 and 5-9), the logic level
 * threshold can be set independently.
 *
 * The threshold can be set to values that are usable for systems with
 * different voltage levels, e.g. for 1.8V or 3.3V systems.
 *
 * The actual threshold value is always the middle of the values below.
 * E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
 * means that values <= 0.9V are considered to be a logic 0/low, and
 * values > 0.9V are considered to be a logic 1/high.
 *
 *  - 1.2V system: threshold = 0.6V
 *  - 1.5V system: threshold = 0.75V
 *  - 1.8V system: threshold = 0.9V
 *  - 2.8V system: threshold = 1.4V
 *  - 3.3V system: threshold = 1.65V
 */
#define THRESHOLD_1_2V_SYSTEM 0x2e
#define THRESHOLD_1_5V_SYSTEM 0x39
#define THRESHOLD_1_8V_SYSTEM 0x45
#define THRESHOLD_2_8V_SYSTEM 0x6c
#define THRESHOLD_3_3V_SYSTEM 0x7f

static int scanaplus_write(struct dev_context *devc, uint8_t *buf, int size)
{
	int i, bytes_written;
	GString *s;

	/* Note: Caller checks devc, devc->ftdic, buf, size. */

	s = g_string_sized_new(100);
	g_string_printf(s, "Writing %d bytes: ", size);
	for (i = 0; i < size; i++)
		g_string_append_printf(s, "0x%02x ", buf[i]);
	sr_spew("%s", s->str);
	g_string_free(s, TRUE);

	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	if (bytes_written < 0) {
		sr_err("Failed to write FTDI data (%d): %s.",
		       bytes_written, ftdi_get_error_string(devc->ftdic));
	} else if (bytes_written != size) {
		sr_err("FTDI write error, only %d/%d bytes written: %s.",
		       bytes_written, size, ftdi_get_error_string(devc->ftdic));
	}

	return bytes_written;
}

SR_PRIV int scanaplus_close(struct dev_context *devc)
{
	int ret;

	/* Note: Caller checks devc and devc->ftdic. */

	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
		sr_err("Failed to close FTDI device (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	return SR_OK;
}

static void scanaplus_uncompress_block(struct dev_context *devc,
				       uint64_t num_bytes)
{
	uint64_t i, j;
	uint8_t num_samples, low, high;

	for (i = 0; i < num_bytes; i += 2) {
		num_samples = devc->compressed_buf[i + 0] >> 1;

		low = devc->compressed_buf[i + 0] & (1 << 0);
		high = devc->compressed_buf[i + 1];

		for (j = 0; j < num_samples; j++) {
			devc->sample_buf[devc->bytes_received++] = high;
			devc->sample_buf[devc->bytes_received++] = low;
		}
	}
}

static void send_samples(const struct sr_dev_inst *sdi, uint64_t samples_to_send)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct dev_context *devc;

	devc = sdi->priv;

	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = samples_to_send * 2;
	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
	logic.data = devc->sample_buf;
	sr_session_send(sdi, &packet);

	devc->samples_sent += samples_to_send;
	devc->bytes_received -= samples_to_send * 2;
}

SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
{
	int ret;
	uint16_t val1, val2;

	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
		sr_err("Failed to read EEPROM index 16 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
		sr_err("Failed to read EEPROM index 17 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	/*
	 * Note: Bit 7 of the three bytes must not be used, apparently.
	 *
	 * Even though the three bits can be either 0 or 1 (we've seen both
	 * in actual ScanaPLUS devices), the device ID as sent to the FPGA
	 * has bit 7 of each byte zero'd out.
	 *
	 * It is unknown whether bit 7 of these bytes has any meaning,
	 * whether it's used somewhere, or whether it can be simply ignored.
	 */
	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);

	return SR_OK;
}

static int scanaplus_clear_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

static int scanaplus_send_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = devc->devid[0];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = devc->devid[1];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = devc->devid[2];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_init(struct dev_context *devc)
{
	int i;
	uint8_t buf[8];

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x89;
	buf[1] = 0x64;
	buf[2] = 0x8a;
	buf[3] = 0x64;
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8d;
	buf[1] = 0x01;
	buf[2] = 0x8d;
	buf[3] = 0x05;
	buf[4] = 0x8d;
	buf[5] = 0x01;
	buf[6] = 0x8d;
	buf[7] = 0x02;
	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
		return SR_ERR;

	for (i = 0; i < 57; i++) {
		buf[0] = 0x8d;
		buf[1] = 0x06;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;

		buf[0] = 0x8d;
		buf[1] = 0x02;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;
	}

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
{
	uint8_t buf[4];

	/* Threshold and differential channel settings not yet implemented. */

	buf[0] = 0x89;
	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
	buf[2] = 0x8a;
	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	if (scanaplus_clear_device_id(devc) < 0)
		return SR_ERR;

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
{
	int bytes_read;
	struct sr_dev_inst *sdi;
	struct dev_context *devc;
	uint64_t max, n;

	(void)fd;
	(void)revents;

	if (!(sdi = cb_data))
		return TRUE;

	if (!(devc = sdi->priv))
		return TRUE;

	if (!devc->ftdic)
		return TRUE;

	/* Get a block of data. */
	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
				    COMPRESSED_BUF_SIZE);
	if (bytes_read < 0) {
		sr_err("Failed to read FTDI data (%d): %s.",
		       bytes_read, ftdi_get_error_string(devc->ftdic));
		sr_dev_acquisition_stop(sdi);
		return FALSE;
	}
	if (bytes_read == 0) {
		sr_spew("Received 0 bytes, nothing to do.");
		return TRUE;
	}

	/*
	 * After a ScanaPLUS acquisition starts, a bunch of samples will be
	 * returned as all-zero, no matter which signals are actually present
	 * on the channels. This is probably due to the FPGA reconfiguring some
	 * of its internal state/config during this time.
	 *
	 * As far as we know there is apparently no way for the PC-side to
	 * know when this "reconfiguration" starts or ends. The FTDI chip
	 * will return all-zero "dummy" samples during this time, which is
	 * indistinguishable from actual all-zero samples.
	 *
	 * We currently simply ignore the first 64kB of data after an
	 * acquisition starts. Empirical tests have shown that the
	 * "reconfigure" time is a lot less than that usually.
	 */
	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
		/* Ignore the first 64kB of data of every acquisition. */
		sr_spew("Ignoring first 64kB chunk of data.");
		devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
		return TRUE;
	}

	/* TODO: Handle bytes_read which is not a multiple of 2? */
	scanaplus_uncompress_block(devc, bytes_read);

	n = devc->samples_sent + (devc->bytes_received / 2);
	max = (SR_MHZ(100) / 1000) * devc->limit_msec;

	if (devc->limit_samples && (n >= devc->limit_samples)) {
		send_samples(sdi, devc->limit_samples - devc->samples_sent);
		sr_info("Requested number of samples reached.");
		sr_dev_acquisition_stop(sdi);
		return TRUE;
	} else if (devc->limit_msec && (n >= max)) {
		send_samples(sdi, max - devc->samples_sent);
		sr_info("Requested time limit reached.");
		sr_dev_acquisition_stop(sdi);
		return TRUE;
	} else {
		send_samples(sdi, devc->bytes_received / 2);
	}

	return TRUE;
}
Commit	Line	Data
fdf4a1f5 UH	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
2ea1fdf1	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
fdf4a1f5 UH	18	*/
fdf4a1f5 UH	19
6ec6c43b	20	#include <config.h>
fdf4a1f5 UH	21	#include "protocol.h"
fdf4a1f5 UH	22
ab4bb6eb UH	23	/*
	24	* Logic level thresholds.
	25	*
	26	* For each of the two channel groups (1-4 and 5-9), the logic level
	27	* threshold can be set independently.
	28	*
	29	* The threshold can be set to values that are usable for systems with
	30	* different voltage levels, e.g. for 1.8V or 3.3V systems.
	31	*
	32	* The actual threshold value is always the middle of the values below.
	33	* E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
	34	* means that values <= 0.9V are considered to be a logic 0/low, and
	35	* values > 0.9V are considered to be a logic 1/high.
	36	*
	37	* - 1.2V system: threshold = 0.6V
	38	* - 1.5V system: threshold = 0.75V
	39	* - 1.8V system: threshold = 0.9V
	40	* - 2.8V system: threshold = 1.4V
	41	* - 3.3V system: threshold = 1.65V
	42	*/
	43	#define THRESHOLD_1_2V_SYSTEM 0x2e
	44	#define THRESHOLD_1_5V_SYSTEM 0x39
	45	#define THRESHOLD_1_8V_SYSTEM 0x45
	46	#define THRESHOLD_2_8V_SYSTEM 0x6c
	47	#define THRESHOLD_3_3V_SYSTEM 0x7f
	48
	49	static int scanaplus_write(struct dev_context devc, uint8_t buf, int size)
	50	{
	51	int i, bytes_written;
	52	GString *s;
	53
	54	/* Note: Caller checks devc, devc->ftdic, buf, size. */
	55
	56	s = g_string_sized_new(100);
	57	g_string_printf(s, "Writing %d bytes: ", size);
	58	for (i = 0; i < size; i++)
	59	g_string_append_printf(s, "0x%02x ", buf[i]);
	60	sr_spew("%s", s->str);
	61	g_string_free(s, TRUE);
	62
	63	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	64	if (bytes_written < 0) {
	65	sr_err("Failed to write FTDI data (%d): %s.",
	66	bytes_written, ftdi_get_error_string(devc->ftdic));
	67	} else if (bytes_written != size) {
	68	sr_err("FTDI write error, only %d/%d bytes written: %s.",
	69	bytes_written, size, ftdi_get_error_string(devc->ftdic));
	70	}
	71
	72	return bytes_written;
	73	}
	74
	75	SR_PRIV int scanaplus_close(struct dev_context *devc)
	76	{
	77	int ret;
	78
	79	/* Note: Caller checks devc and devc->ftdic. */
	80
	81	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
	82	sr_err("Failed to close FTDI device (%d): %s.",
	83	ret, ftdi_get_error_string(devc->ftdic));
	84	return SR_ERR;
	85	}
	86
87	return SR_OK;
88	}
89
90	static void scanaplus_uncompress_block(struct dev_context *devc,
91	uint64_t num_bytes)
fdf4a1f5	92	{
ab4bb6eb UH	93	uint64_t i, j;
	94	uint8_t num_samples, low, high;
	95
	96	for (i = 0; i < num_bytes; i += 2) {
	97	num_samples = devc->compressed_buf[i + 0] >> 1;
	98
	99	low = devc->compressed_buf[i + 0] & (1 << 0);
	100	high = devc->compressed_buf[i + 1];
	101
	102	for (j = 0; j < num_samples; j++) {
	103	devc->sample_buf[devc->bytes_received++] = high;
	104	devc->sample_buf[devc->bytes_received++] = low;
	105	}
	106	}
	107	}
	108
695dc859	109	static void send_samples(const struct sr_dev_inst *sdi, uint64_t samples_to_send)
ab4bb6eb UH	110	{
	111	struct sr_datafeed_packet packet;
	112	struct sr_datafeed_logic logic;
695dc859 UH	113	struct dev_context *devc;
	114
	115	devc = sdi->priv;
ab4bb6eb UH	116
	117	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);
	118
	119	packet.type = SR_DF_LOGIC;
	120	packet.payload = &logic;
	121	logic.length = samples_to_send * 2;
ba7dd8bb	122	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
ab4bb6eb	123	logic.data = devc->sample_buf;
695dc859	124	sr_session_send(sdi, &packet);
ab4bb6eb UH	125
	126	devc->samples_sent += samples_to_send;
	127	devc->bytes_received -= samples_to_send * 2;
	128	}
	129
	130	SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
	131	{
	132	int ret;
	133	uint16_t val1, val2;
	134
	135	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	136	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
	137	sr_err("Failed to read EEPROM index 16 (%d): %s.",
	138	ret, ftdi_get_error_string(devc->ftdic));
	139	return SR_ERR;
	140	}
	141	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
	142	sr_err("Failed to read EEPROM index 17 (%d): %s.",
	143	ret, ftdi_get_error_string(devc->ftdic));
	144	return SR_ERR;
	145	}
	146
	147	/*
	148	* Note: Bit 7 of the three bytes must not be used, apparently.
	149	*
	150	* Even though the three bits can be either 0 or 1 (we've seen both
	151	* in actual ScanaPLUS devices), the device ID as sent to the FPGA
	152	* has bit 7 of each byte zero'd out.
	153	*
	154	* It is unknown whether bit 7 of these bytes has any meaning,
	155	* whether it's used somewhere, or whether it can be simply ignored.
	156	*/
	157	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	158	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	159	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);
	160
	161	return SR_OK;
	162	}
	163
	164	static int scanaplus_clear_device_id(struct dev_context *devc)
	165	{
	166	uint8_t buf[2];
	167
	168	buf[0] = 0x8c;
	169	buf[1] = 0x00;
	170	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	171	return SR_ERR;
	172
	173	buf[0] = 0x8e;
	174	buf[1] = 0x00;
	175	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	176	return SR_ERR;
	177
	178	buf[0] = 0x8f;
	179	buf[1] = 0x00;
	180	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	181	return SR_ERR;
	182
	183	return SR_OK;
	184	}
	185
	186	static int scanaplus_send_device_id(struct dev_context *devc)
	187	{
	188	uint8_t buf[2];
189
190	buf[0] = 0x8c;
191	buf[1] = devc->devid[0];
192	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
193	return SR_ERR;
194
195	buf[0] = 0x8e;
196	buf[1] = devc->devid[1];
197	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
198	return SR_ERR;
199
200	buf[0] = 0x8f;
201	buf[1] = devc->devid[2];
202	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
203	return SR_ERR;
204
205	return SR_OK;
206	}
207
208	SR_PRIV int scanaplus_init(struct dev_context *devc)
209	{
210	int i;
211	uint8_t buf[8];
212
213	buf[0] = 0x88;
214	buf[1] = 0x41;
215	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
216	return SR_ERR;
217
218	buf[0] = 0x89;
219	buf[1] = 0x64;
220	buf[2] = 0x8a;
221	buf[3] = 0x64;
222	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
223	return SR_ERR;
224
225	buf[0] = 0x88;
226	buf[1] = 0x41;
227	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
228	return SR_ERR;
229
230	buf[0] = 0x88;
231	buf[1] = 0x40;
232	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
233	return SR_ERR;
234
235	buf[0] = 0x8d;
236	buf[1] = 0x01;
237	buf[2] = 0x8d;
238	buf[3] = 0x05;
239	buf[4] = 0x8d;
240	buf[5] = 0x01;
241	buf[6] = 0x8d;
242	buf[7] = 0x02;
243	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
244	return SR_ERR;
245
246	for (i = 0; i < 57; i++) {
247	buf[0] = 0x8d;
248	buf[1] = 0x06;
249	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
250	return SR_ERR;
251
252	buf[0] = 0x8d;
253	buf[1] = 0x02;
254	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
255	return SR_ERR;
256	}
257
258	if (scanaplus_send_device_id(devc) < 0)
259	return SR_ERR;
260
261	buf[0] = 0x88;
262	buf[1] = 0x40;
263	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
264	return SR_ERR;
265
266	return SR_OK;
267	}
268
269	SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
270	{
271	uint8_t buf[4];
272
ba7dd8bb	273	/* Threshold and differential channel settings not yet implemented. */
ab4bb6eb UH	274
ab4bb6eb UH	275	buf[0] = 0x89;
ba7dd8bb	276	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
ab4bb6eb	277	buf[2] = 0x8a;
ba7dd8bb	278	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
ab4bb6eb UH	279	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
	280	return SR_ERR;
	281
	282	buf[0] = 0x88;
ba7dd8bb	283	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
ab4bb6eb UH	284	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	285	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	286	return SR_ERR;
	287
	288	if (scanaplus_clear_device_id(devc) < 0)
	289	return SR_ERR;
	290
	291	if (scanaplus_send_device_id(devc) < 0)
	292	return SR_ERR;
	293
	294	return SR_OK;
	295	}
	296
	297	SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
	298	{
	299	int bytes_read;
	300	struct sr_dev_inst *sdi;
fdf4a1f5	301	struct dev_context *devc;
ab4bb6eb	302	uint64_t max, n;
fdf4a1f5 UH	303
fdf4a1f5 UH	304	(void)fd;
ab4bb6eb	305	(void)revents;
fdf4a1f5 UH	306
	307	if (!(sdi = cb_data))
	308	return TRUE;
	309
	310	if (!(devc = sdi->priv))
	311	return TRUE;
	312
ab4bb6eb UH	313	if (!devc->ftdic)
	314	return TRUE;
	315
	316	/* Get a block of data. */
	317	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
	318	COMPRESSED_BUF_SIZE);
	319	if (bytes_read < 0) {
	320	sr_err("Failed to read FTDI data (%d): %s.",
	321	bytes_read, ftdi_get_error_string(devc->ftdic));
d2f7c417	322	sr_dev_acquisition_stop(sdi);
ab4bb6eb UH	323	return FALSE;
	324	}
	325	if (bytes_read == 0) {
	326	sr_spew("Received 0 bytes, nothing to do.");
	327	return TRUE;
	328	}
	329
	330	/*
	331	* After a ScanaPLUS acquisition starts, a bunch of samples will be
	332	* returned as all-zero, no matter which signals are actually present
ba7dd8bb	333	* on the channels. This is probably due to the FPGA reconfiguring some
ab4bb6eb UH	334	* of its internal state/config during this time.
	335	*
	336	* As far as we know there is apparently no way for the PC-side to
	337	* know when this "reconfiguration" starts or ends. The FTDI chip
	338	* will return all-zero "dummy" samples during this time, which is
	339	* indistinguishable from actual all-zero samples.
	340	*
	341	* We currently simply ignore the first 64kB of data after an
	342	* acquisition starts. Empirical tests have shown that the
	343	* "reconfigure" time is a lot less than that usually.
	344	*/
	345	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
	346	/* Ignore the first 64kB of data of every acquisition. */
	347	sr_spew("Ignoring first 64kB chunk of data.");
	348	devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
	349	return TRUE;
	350	}
	351
	352	/* TODO: Handle bytes_read which is not a multiple of 2? */
	353	scanaplus_uncompress_block(devc, bytes_read);
	354
	355	n = devc->samples_sent + (devc->bytes_received / 2);
	356	max = (SR_MHZ(100) / 1000) * devc->limit_msec;
	357
	358	if (devc->limit_samples && (n >= devc->limit_samples)) {
695dc859	359	send_samples(sdi, devc->limit_samples - devc->samples_sent);
ab4bb6eb	360	sr_info("Requested number of samples reached.");
d2f7c417	361	sr_dev_acquisition_stop(sdi);
ab4bb6eb UH	362	return TRUE;
ab4bb6eb UH	363	} else if (devc->limit_msec && (n >= max)) {
695dc859	364	send_samples(sdi, max - devc->samples_sent);
ab4bb6eb	365	sr_info("Requested time limit reached.");
d2f7c417	366	sr_dev_acquisition_stop(sdi);
ab4bb6eb UH	367	return TRUE;
ab4bb6eb UH	368	} else {
695dc859	369	send_samples(sdi, devc->bytes_received / 2);
fdf4a1f5 UH	370	}
	371
	372	return TRUE;
	373	}