[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

#define FW_BUFSIZE (4 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *filename)
{
	FILE *fw;
	GStatBuf st;
	struct sr_usb_dev_inst *usb;
	int chunksize, result, ret;
	unsigned char *buf;
	int sum, transferred;
	uint8_t cmd[3];

	sr_dbg("Uploading FPGA firmware at %s.", filename);

	usb = sdi->conn;
	if (g_stat(filename, &st) < 0) {
		sr_err("Unable to upload FPGA firmware: %s", g_strerror(errno));
		return SR_ERR;
	}

	/* Tell the device firmware is coming. */
	memset(cmd, 0, sizeof(cmd));
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		return SR_ERR;
	}
	buf = g_malloc(FW_BUFSIZE);

	if (!(fw = g_fopen(filename, "rb"))) {
		sr_err("Unable to open %s for reading: %s.", filename, g_strerror(errno));
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	sum = 0;
	result = SR_OK;
	while (1) {
		if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %d/%" PRIu64 " bytes.",
			sum, (uint64_t)st.st_size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	fclose(fw);
	g_free(buf);
	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	devc = sdi->priv;
	mode.flags = 0;
	mode.sample_delay_h = mode.sample_delay_l = 0;
	if (devc->sample_wide)
		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");
	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	WL32(&cfg.count_header, DS_CFG_COUNT);
	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			c, 3, USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	/*
	 * 15	1 = internal test mode
	 * 14	1 = external test mode
	 * 13	1 = loopback test mode
	 * 8-12	unused
	 * 7	1 = analog mode
	 * 6	1 = samplerate 400MHz
	 * 5	1 = samplerate 200MHz or analog mode
	 * 4	0 = logic, 1 = dso or analog
	 * 2-3	unused
	 * 1	0 = internal clock, 1 = external clock
	 * 0	1 = trigger enabled
	 */
	v16 = 0x0000;
	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
		v16 = 1 << 15;
	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
		v16 = 1 << 14;
	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
		v16 = 1 << 13;
	if (devc->dslogic_external_clock)
		v16 |= 1 << 2;
	WL16(&cfg.mode, v16);

	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <sys/types.h>
	23	#include <sys/stat.h>
	24	#include <unistd.h>
	25	#include <errno.h>
	26	#include <math.h>
	27	#include <glib.h>
	28	#include <glib/gstdio.h>
	29	#include "protocol.h"
	30	#include "dslogic.h"
	31
1a46cc62 UH	32	#define FW_BUFSIZE (4 * 1024)
1a46cc62 UH	33
4df5739a UH	34	#define FPGA_UPLOAD_DELAY (10 * 1000)
	35
	36	#define USB_TIMEOUT (3 * 1000)
	37
b9d53092 BV	38	int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
	39	const char *filename)
	40	{
	41	FILE *fw;
6433156c	42	GStatBuf st;
b9d53092 BV	43	struct sr_usb_dev_inst *usb;
	44	int chunksize, result, ret;
	45	unsigned char *buf;
	46	int sum, transferred;
d93c1470	47	uint8_t cmd[3];
b9d53092 BV	48
	49	sr_dbg("Uploading FPGA firmware at %s.", filename);
	50
	51	usb = sdi->conn;
6433156c	52	if (g_stat(filename, &st) < 0) {
7237e912	53	sr_err("Unable to upload FPGA firmware: %s", g_strerror(errno));
b9d53092 BV	54	return SR_ERR;
	55	}
	56
	57	/* Tell the device firmware is coming. */
d93c1470	58	memset(cmd, 0, sizeof(cmd));
b9d53092 BV	59	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
b9d53092 BV	60	LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
d93c1470	61	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092 BV	62	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
	63	return SR_ERR;
	64	}
	65	buf = g_malloc(FW_BUFSIZE);
	66
98fec29e	67	if (!(fw = g_fopen(filename, "rb"))) {
7237e912	68	sr_err("Unable to open %s for reading: %s.", filename, g_strerror(errno));
b9d53092 BV	69	return SR_ERR;
	70	}
	71
	72	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	73	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092 BV	74
	75	sum = 0;
	76	result = SR_OK;
	77	while (1) {
	78	if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
	79	break;
	80
	81	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	82	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	83	sr_err("Unable to configure FPGA firmware: %s.",
	84	libusb_error_name(ret));
	85	result = SR_ERR;
	86	break;
	87	}
	88	sum += transferred;
6433156c DE	89	sr_spew("Uploaded %d/%" PRIu64 " bytes.",
6433156c DE	90	sum, (uint64_t)st.st_size);
b9d53092 BV	91
	92	if (transferred != chunksize) {
	93	sr_err("Short transfer while uploading FPGA firmware.");
	94	result = SR_ERR;
	95	break;
	96	}
	97	}
	98	fclose(fw);
	99	g_free(buf);
	100	if (result == SR_OK)
	101	sr_dbg("FPGA firmware upload done.");
	102
	103	return result;
	104	}
	105
	106	int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
	107	{
	108	struct dev_context *devc;
	109	struct sr_usb_dev_inst *usb;
	110	struct dslogic_mode mode;
	111	int ret;
	112
	113	devc = sdi->priv;
	114	mode.flags = 0;
	115	mode.sample_delay_h = mode.sample_delay_l = 0;
	116	if (devc->sample_wide)
	117	mode.flags \|= DS_START_FLAGS_SAMPLE_WIDE;
	118
	119	usb = sdi->conn;
	120	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	121	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	122	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	123	if (ret < 0) {
	124	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	125	return SR_ERR;
	126	}
	127
	128	return SR_OK;
	129	}
	130
	131	int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
	132	{
	133	struct sr_usb_dev_inst *usb;
	134	struct dslogic_mode mode;
	135	int ret;
	136
	137	mode.flags = DS_START_FLAGS_STOP;
	138	mode.sample_delay_h = mode.sample_delay_l = 0;
	139
	140	usb = sdi->conn;
	141	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	142	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	143	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	144	if (ret < 0) {
	145	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	146	return SR_ERR;
	147	}
	148
	149	return SR_OK;
	150	}
	151
	152	int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
	153	{
	154	struct dev_context *devc;
	155	struct sr_usb_dev_inst *usb;
	156	uint8_t c[3];
	157	struct dslogic_fpga_config cfg;
	158	uint16_t v16;
	159	uint32_t v32;
	160	int transferred, len, ret;
	161
	162	sr_dbg("Configuring FPGA.");
	163	usb = sdi->conn;
	164	devc = sdi->priv;
	165
	166	WL32(&cfg.sync, DS_CFG_START);
	167	WL16(&cfg.mode_header, DS_CFG_MODE);
	168	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	169	WL32(&cfg.count_header, DS_CFG_COUNT);
	170	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	171	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	172	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	173	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	174	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	175	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	176	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	177	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	178	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	179	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	180	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	181	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	182	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	183	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	184	WL32(&cfg.end_sync, DS_CFG_END);
	185
	186	/* Pass in the length of a fixed-size struct. Really. */
	187	len = sizeof(struct dslogic_fpga_config) / 2;
	188	c[0] = len & 0xff;
	189	c[1] = (len >> 8) & 0xff;
	190	c[2] = (len >> 16) & 0xff;
	191
	192	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	193	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
4df5739a	194	c, 3, USB_TIMEOUT);
b9d53092 BV	195	if (ret < 0) {
	196	sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
	197	return SR_ERR;
	198	}
	199
	200	/*
	201	* 15 1 = internal test mode
	202	* 14 1 = external test mode
	203	* 13 1 = loopback test mode
	204	* 8-12 unused
	205	* 7 1 = analog mode
	206	* 6 1 = samplerate 400MHz
	207	* 5 1 = samplerate 200MHz or analog mode
	208	* 4 0 = logic, 1 = dso or analog
	209	* 2-3 unused
	210	* 1 0 = internal clock, 1 = external clock
	211	* 0 1 = trigger enabled
	212	*/
	213	v16 = 0x0000;
	214	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
	215	v16 = 1 << 15;
	216	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
	217	v16 = 1 << 14;
	218	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
	219	v16 = 1 << 13;
	220	if (devc->dslogic_external_clock)
	221	v16 \|= 1 << 2;
	222	WL16(&cfg.mode, v16);
	223
	224	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	225	WL32(&cfg.divider, v32);
	226	WL32(&cfg.count, devc->limit_samples);
	227
	228	len = sizeof(struct dslogic_fpga_config);
	229	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	230	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	231	if (ret < 0 \|\| transferred != len) {
	232	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	233	return SR_ERR;
	234	}
	235
	236	return SR_OK;
	237	}