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b9d53092 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
6ec6c43b | 21 | #include <config.h> |
b9d53092 BV |
22 | #include <math.h> |
23 | #include <glib.h> | |
24 | #include <glib/gstdio.h> | |
25 | #include "protocol.h" | |
26 | #include "dslogic.h" | |
27 | ||
3f0ff412 DA |
28 | /* |
29 | * This should be larger than the FPGA bitstream image so that it'll get | |
30 | * uploaded in one big operation. There seem to be issues when uploading | |
31 | * it in chunks. | |
32 | */ | |
33 | #define FW_BUFSIZE (1024 * 1024) | |
1a46cc62 | 34 | |
4df5739a UH |
35 | #define FPGA_UPLOAD_DELAY (10 * 1000) |
36 | ||
37 | #define USB_TIMEOUT (3 * 1000) | |
38 | ||
3566348b | 39 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi) |
b9d53092 | 40 | { |
3566348b | 41 | const char *name = NULL; |
8e2d6c9d DE |
42 | uint64_t sum; |
43 | struct sr_resource bitstream; | |
44 | struct drv_context *drvc; | |
3566348b | 45 | struct dev_context *devc; |
b9d53092 | 46 | struct sr_usb_dev_inst *usb; |
b9d53092 | 47 | unsigned char *buf; |
8e2d6c9d DE |
48 | ssize_t chunksize; |
49 | int transferred; | |
50 | int result, ret; | |
cd189a44 | 51 | const uint8_t cmd[3] = {0, 0, 0}; |
b9d53092 | 52 | |
8e2d6c9d | 53 | drvc = sdi->driver->context; |
3566348b | 54 | devc = sdi->priv; |
b9d53092 | 55 | usb = sdi->conn; |
8e2d6c9d | 56 | |
3566348b | 57 | if (!strcmp(devc->profile->model, "DSLogic")) { |
1ee70746 | 58 | if (devc->cur_threshold < 1.40) |
3566348b JH |
59 | name = DSLOGIC_FPGA_FIRMWARE_3V3; |
60 | else | |
61 | name = DSLOGIC_FPGA_FIRMWARE_5V; | |
62 | } else if (!strcmp(devc->profile->model, "DSLogic Pro")){ | |
63 | name = DSLOGIC_PRO_FPGA_FIRMWARE; | |
64 | } else if (!strcmp(devc->profile->model, "DSLogic Plus")){ | |
65 | name = DSLOGIC_PLUS_FPGA_FIRMWARE; | |
66 | } else if (!strcmp(devc->profile->model, "DSLogic Basic")){ | |
67 | name = DSLOGIC_BASIC_FPGA_FIRMWARE; | |
68 | } else if (!strcmp(devc->profile->model, "DSCope")) { | |
69 | name = DSCOPE_FPGA_FIRMWARE; | |
70 | } else { | |
71 | sr_err("Failed to select FPGA firmware."); | |
72 | return SR_ERR; | |
73 | } | |
74 | ||
8e2d6c9d DE |
75 | sr_dbg("Uploading FPGA firmware '%s'.", name); |
76 | ||
77 | result = sr_resource_open(drvc->sr_ctx, &bitstream, | |
78 | SR_RESOURCE_FIRMWARE, name); | |
79 | if (result != SR_OK) | |
80 | return result; | |
b9d53092 BV |
81 | |
82 | /* Tell the device firmware is coming. */ | |
83 | if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
9d71f815 | 84 | LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, |
d93c1470 | 85 | (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) { |
b9d53092 | 86 | sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); |
8e2d6c9d | 87 | sr_resource_close(drvc->sr_ctx, &bitstream); |
b9d53092 BV |
88 | return SR_ERR; |
89 | } | |
90 | ||
91 | /* Give the FX2 time to get ready for FPGA firmware upload. */ | |
4df5739a | 92 | g_usleep(FPGA_UPLOAD_DELAY); |
b9d53092 | 93 | |
8e2d6c9d | 94 | buf = g_malloc(FW_BUFSIZE); |
b9d53092 BV |
95 | sum = 0; |
96 | result = SR_OK; | |
97 | while (1) { | |
8e2d6c9d DE |
98 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, |
99 | buf, FW_BUFSIZE); | |
100 | if (chunksize < 0) | |
101 | result = SR_ERR; | |
102 | if (chunksize <= 0) | |
b9d53092 BV |
103 | break; |
104 | ||
105 | if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 106 | buf, chunksize, &transferred, USB_TIMEOUT)) < 0) { |
b9d53092 BV |
107 | sr_err("Unable to configure FPGA firmware: %s.", |
108 | libusb_error_name(ret)); | |
109 | result = SR_ERR; | |
110 | break; | |
111 | } | |
112 | sum += transferred; | |
8e2d6c9d DE |
113 | sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.", |
114 | sum, bitstream.size); | |
b9d53092 BV |
115 | |
116 | if (transferred != chunksize) { | |
117 | sr_err("Short transfer while uploading FPGA firmware."); | |
118 | result = SR_ERR; | |
119 | break; | |
120 | } | |
121 | } | |
b9d53092 | 122 | g_free(buf); |
8e2d6c9d DE |
123 | sr_resource_close(drvc->sr_ctx, &bitstream); |
124 | ||
b9d53092 BV |
125 | if (result == SR_OK) |
126 | sr_dbg("FPGA firmware upload done."); | |
127 | ||
128 | return result; | |
129 | } | |
130 | ||
8e2d6c9d | 131 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 | 132 | { |
b9d53092 BV |
133 | struct sr_usb_dev_inst *usb; |
134 | struct dslogic_mode mode; | |
135 | int ret; | |
136 | ||
adcb9951 | 137 | mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE; |
b9d53092 | 138 | mode.sample_delay_h = mode.sample_delay_l = 0; |
b9d53092 BV |
139 | |
140 | usb = sdi->conn; | |
141 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
142 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 143 | (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT); |
b9d53092 BV |
144 | if (ret < 0) { |
145 | sr_err("Failed to send start command: %s.", libusb_error_name(ret)); | |
146 | return SR_ERR; | |
147 | } | |
148 | ||
149 | return SR_OK; | |
150 | } | |
151 | ||
8e2d6c9d | 152 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi) |
b9d53092 BV |
153 | { |
154 | struct sr_usb_dev_inst *usb; | |
155 | struct dslogic_mode mode; | |
156 | int ret; | |
157 | ||
158 | mode.flags = DS_START_FLAGS_STOP; | |
159 | mode.sample_delay_h = mode.sample_delay_l = 0; | |
160 | ||
161 | usb = sdi->conn; | |
162 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
163 | LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, | |
4df5739a | 164 | (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT); |
b9d53092 BV |
165 | if (ret < 0) { |
166 | sr_err("Failed to send stop command: %s.", libusb_error_name(ret)); | |
167 | return SR_ERR; | |
168 | } | |
169 | ||
170 | return SR_OK; | |
171 | } | |
172 | ||
3db03efa DA |
173 | /* |
174 | * Get the session trigger and configure the FPGA structure | |
175 | * accordingly. | |
176 | */ | |
2f3cf5c2 | 177 | static void dslogic_set_trigger(const struct sr_dev_inst *sdi, |
3db03efa DA |
178 | struct dslogic_fpga_config *cfg) |
179 | { | |
180 | struct sr_trigger *trigger; | |
181 | struct sr_trigger_stage *stage; | |
182 | struct sr_trigger_match *match; | |
183 | struct dev_context *devc; | |
184 | const GSList *l, *m; | |
2f3cf5c2 | 185 | int num_enabled_channels = 0, num_trigger_stages = 0; |
3db03efa | 186 | int channelbit, i = 0; |
2f3cf5c2 | 187 | uint32_t trigger_point; |
3db03efa | 188 | |
9803346f UH |
189 | devc = sdi->priv; |
190 | ||
e40ee26b JH |
191 | cfg->ch_en = 0; |
192 | for (l = sdi->channels; l; l = l->next) { | |
193 | const struct sr_channel *const probe = (struct sr_channel *)l->data; | |
2f3cf5c2 JH |
194 | if (probe->enabled) { |
195 | num_enabled_channels++; | |
196 | cfg->ch_en |= 1 << probe->index; | |
197 | } | |
e40ee26b JH |
198 | } |
199 | ||
3db03efa DA |
200 | cfg->trig_mask0[0] = 0xffff; |
201 | cfg->trig_mask1[0] = 0xffff; | |
202 | ||
203 | cfg->trig_value0[0] = 0; | |
204 | cfg->trig_value1[0] = 0; | |
205 | ||
206 | cfg->trig_edge0[0] = 0; | |
207 | cfg->trig_edge1[0] = 0; | |
208 | ||
2f3cf5c2 JH |
209 | cfg->trig_logic0[0] = 2; |
210 | cfg->trig_logic1[0] = 2; | |
3db03efa | 211 | |
e40ee26b | 212 | cfg->trig_count[0] = 0; |
3db03efa | 213 | |
2f3cf5c2 | 214 | cfg->trig_glb = num_enabled_channels << 4; |
4237fbca | 215 | |
adcb9951 | 216 | for (i = 1; i < NUM_TRIGGER_STAGES; i++) { |
2f3cf5c2 JH |
217 | cfg->trig_mask0[i] = 0xffff; |
218 | cfg->trig_mask1[i] = 0xffff; | |
4237fbca DA |
219 | cfg->trig_value0[i] = 0; |
220 | cfg->trig_value1[i] = 0; | |
221 | cfg->trig_edge0[i] = 0; | |
222 | cfg->trig_edge1[i] = 0; | |
4237fbca DA |
223 | cfg->trig_logic0[i] = 2; |
224 | cfg->trig_logic1[i] = 2; | |
e40ee26b | 225 | cfg->trig_count[i] = 0; |
4237fbca DA |
226 | } |
227 | ||
2f3cf5c2 JH |
228 | trigger_point = (devc->capture_ratio * devc->limit_samples) / 100; |
229 | if (trigger_point < DSLOGIC_ATOMIC_SAMPLES) | |
230 | trigger_point = DSLOGIC_ATOMIC_SAMPLES; | |
231 | const uint32_t mem_depth = devc->profile->mem_depth; | |
232 | const uint32_t max_trigger_point = devc->continuous_mode ? ((mem_depth * 10) / 100) : | |
233 | ((mem_depth * DS_MAX_TRIG_PERCENT) / 100); | |
234 | if (trigger_point > max_trigger_point) | |
235 | trigger_point = max_trigger_point; | |
236 | cfg->trig_pos = trigger_point & ~(DSLOGIC_ATOMIC_SAMPLES - 1); | |
4237fbca | 237 | |
9803346f | 238 | if (!(trigger = sr_session_trigger_get(sdi->session))) { |
4237fbca | 239 | sr_dbg("No session trigger found"); |
2f3cf5c2 | 240 | return; |
4237fbca | 241 | } |
3db03efa DA |
242 | |
243 | for (l = trigger->stages; l; l = l->next) { | |
244 | stage = l->data; | |
2f3cf5c2 | 245 | num_trigger_stages++; |
3db03efa DA |
246 | for (m = stage->matches; m; m = m->next) { |
247 | match = m->data; | |
248 | if (!match->channel->enabled) | |
249 | /* Ignore disabled channels with a trigger. */ | |
250 | continue; | |
251 | channelbit = 1 << (match->channel->index); | |
3db03efa DA |
252 | /* Simple trigger support (event). */ |
253 | if (match->match == SR_TRIGGER_ONE) { | |
254 | cfg->trig_mask0[0] &= ~channelbit; | |
255 | cfg->trig_mask1[0] &= ~channelbit; | |
256 | cfg->trig_value0[0] |= channelbit; | |
257 | cfg->trig_value1[0] |= channelbit; | |
258 | } else if (match->match == SR_TRIGGER_ZERO) { | |
259 | cfg->trig_mask0[0] &= ~channelbit; | |
260 | cfg->trig_mask1[0] &= ~channelbit; | |
261 | } else if (match->match == SR_TRIGGER_FALLING) { | |
262 | cfg->trig_mask0[0] &= ~channelbit; | |
263 | cfg->trig_mask1[0] &= ~channelbit; | |
264 | cfg->trig_edge0[0] |= channelbit; | |
265 | cfg->trig_edge1[0] |= channelbit; | |
266 | } else if (match->match == SR_TRIGGER_RISING) { | |
267 | cfg->trig_mask0[0] &= ~channelbit; | |
268 | cfg->trig_mask1[0] &= ~channelbit; | |
269 | cfg->trig_value0[0] |= channelbit; | |
270 | cfg->trig_value1[0] |= channelbit; | |
271 | cfg->trig_edge0[0] |= channelbit; | |
272 | cfg->trig_edge1[0] |= channelbit; | |
9803346f | 273 | } else if (match->match == SR_TRIGGER_EDGE) { |
3db03efa DA |
274 | cfg->trig_edge0[0] |= channelbit; |
275 | cfg->trig_edge1[0] |= channelbit; | |
276 | } | |
277 | } | |
278 | } | |
9803346f | 279 | |
2f3cf5c2 | 280 | cfg->trig_glb |= num_trigger_stages; |
9803346f | 281 | |
2f3cf5c2 | 282 | return; |
3db03efa DA |
283 | } |
284 | ||
8e2d6c9d | 285 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) |
b9d53092 BV |
286 | { |
287 | struct dev_context *devc; | |
288 | struct sr_usb_dev_inst *usb; | |
289 | uint8_t c[3]; | |
290 | struct dslogic_fpga_config cfg; | |
291 | uint16_t v16; | |
292 | uint32_t v32; | |
293 | int transferred, len, ret; | |
294 | ||
295 | sr_dbg("Configuring FPGA."); | |
9803346f | 296 | |
b9d53092 BV |
297 | usb = sdi->conn; |
298 | devc = sdi->priv; | |
299 | ||
300 | WL32(&cfg.sync, DS_CFG_START); | |
301 | WL16(&cfg.mode_header, DS_CFG_MODE); | |
e40ee26b JH |
302 | WL16(&cfg.divider_header, DS_CFG_DIVIDER); |
303 | WL16(&cfg.count_header, DS_CFG_COUNT); | |
304 | WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS); | |
b9d53092 | 305 | WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); |
e40ee26b JH |
306 | WL16(&cfg.ch_en_header, DS_CFG_CH_EN); |
307 | WL16(&cfg.trig_header, DS_CFG_TRIG); | |
b9d53092 BV |
308 | WL32(&cfg.end_sync, DS_CFG_END); |
309 | ||
310 | /* Pass in the length of a fixed-size struct. Really. */ | |
311 | len = sizeof(struct dslogic_fpga_config) / 2; | |
312 | c[0] = len & 0xff; | |
313 | c[1] = (len >> 8) & 0xff; | |
314 | c[2] = (len >> 16) & 0xff; | |
315 | ||
316 | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | | |
e40ee26b JH |
317 | LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000, |
318 | c, sizeof(c), USB_TIMEOUT); | |
b9d53092 | 319 | if (ret < 0) { |
9803346f UH |
320 | sr_err("Failed to send FPGA configure command: %s.", |
321 | libusb_error_name(ret)); | |
b9d53092 BV |
322 | return SR_ERR; |
323 | } | |
324 | ||
b9d53092 | 325 | v16 = 0x0000; |
e40ee26b | 326 | |
adcb9951 | 327 | if (devc->mode == DS_OP_INTERNAL_TEST) |
cf398cc0 | 328 | v16 = DS_MODE_INT_TEST; |
adcb9951 | 329 | else if (devc->mode == DS_OP_EXTERNAL_TEST) |
cf398cc0 | 330 | v16 = DS_MODE_EXT_TEST; |
adcb9951 | 331 | else if (devc->mode == DS_OP_LOOPBACK_TEST) |
cf398cc0 | 332 | v16 = DS_MODE_LPB_TEST; |
780c5e24 JH |
333 | |
334 | if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2) | |
335 | v16 |= DS_MODE_HALF_MODE; | |
336 | else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4) | |
337 | v16 |= DS_MODE_QUAR_MODE; | |
338 | ||
adcb9951 | 339 | if (devc->continuous_mode) |
cf398cc0 | 340 | v16 |= DS_MODE_STREAM_MODE; |
adcb9951 | 341 | if (devc->external_clock) { |
cf398cc0 | 342 | v16 |= DS_MODE_CLK_TYPE; |
adcb9951 | 343 | if (devc->clock_edge == DS_EDGE_FALLING) |
cf398cc0 | 344 | v16 |= DS_MODE_CLK_EDGE; |
d9a58763 | 345 | } |
9803346f | 346 | if (devc->limit_samples > DS_MAX_LOGIC_DEPTH * |
176d785d | 347 | ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE) |
adcb9951 | 348 | && !devc->continuous_mode) { |
9803346f UH |
349 | /* Enable RLE for long captures. |
350 | * Without this, captured data present errors. | |
351 | */ | |
cf398cc0 | 352 | v16 |= DS_MODE_RLE_MODE; |
a9a9bfaa | 353 | } |
3fc3fbe4 | 354 | |
b9d53092 | 355 | WL16(&cfg.mode, v16); |
a04b28ce | 356 | v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate); |
b9d53092 | 357 | WL32(&cfg.divider, v32); |
2f3cf5c2 JH |
358 | |
359 | /* Number of 16-sample units. */ | |
360 | WL32(&cfg.count, devc->limit_samples / 16); | |
b9d53092 | 361 | |
3db03efa DA |
362 | dslogic_set_trigger(sdi, &cfg); |
363 | ||
b9d53092 BV |
364 | len = sizeof(struct dslogic_fpga_config); |
365 | ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, | |
4df5739a | 366 | (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT); |
b9d53092 BV |
367 | if (ret < 0 || transferred != len) { |
368 | sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret)); | |
369 | return SR_ERR; | |
370 | } | |
371 | ||
372 | return SR_OK; | |
373 | } | |
a04b28ce | 374 | |
9803346f UH |
375 | static int to_bytes_per_ms(struct dev_context *devc) |
376 | { | |
a04b28ce | 377 | if (devc->cur_samplerate > SR_MHZ(100)) |
adcb9951 JH |
378 | return SR_MHZ(100) / 1000 * 2; |
379 | return devc->cur_samplerate / 1000 * 2; | |
a04b28ce DA |
380 | } |
381 | ||
382 | static size_t get_buffer_size(struct dev_context *devc) | |
383 | { | |
9803346f UH |
384 | size_t s; |
385 | ||
386 | /* | |
387 | * The buffer should be large enough to hold 10ms of data and | |
388 | * a multiple of 512. | |
389 | */ | |
390 | s = 10 * to_bytes_per_ms(devc); | |
391 | // s = to_bytes_per_ms(devc->cur_samplerate); | |
392 | return (s + 511) & ~511; | |
a04b28ce DA |
393 | } |
394 | ||
9803346f UH |
395 | SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc) |
396 | { | |
a04b28ce | 397 | unsigned int n; |
9803346f | 398 | |
a04b28ce | 399 | /* Total buffer size should be able to hold about 100ms of data. */ |
9803346f | 400 | n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc)); |
a04b28ce DA |
401 | sr_info("New calculation: %d", n); |
402 | ||
403 | if (n > NUM_SIMUL_TRANSFERS) | |
404 | return NUM_SIMUL_TRANSFERS; | |
405 | ||
406 | return n; | |
407 | } |