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3ba56876 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
3ba56876 | 8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
3ba56876 | 23 | #include <config.h> |
24 | #include "protocol.h" | |
25 | ||
3ba56876 | 26 | /* |
27 | * Channel numbers seem to go from 1-16, according to this image: | |
28 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
29 | * (the cable has two additional GND pins, and a TI and TO pin) | |
30 | */ | |
31 | static const char *channel_names[] = { | |
32 | "1", "2", "3", "4", "5", "6", "7", "8", | |
33 | "9", "10", "11", "12", "13", "14", "15", "16", | |
34 | }; | |
35 | ||
53a939ab GS |
36 | static const uint32_t scanopts[] = { |
37 | SR_CONF_CONN, | |
38 | }; | |
39 | ||
3ba56876 | 40 | static const uint32_t drvopts[] = { |
41 | SR_CONF_LOGIC_ANALYZER, | |
42 | }; | |
43 | ||
44 | static const uint32_t devopts[] = { | |
45 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
2f7e529c | 46 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
53a939ab | 47 | SR_CONF_CONN | SR_CONF_GET, |
3ba56876 | 48 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
2d8a5089 GS |
49 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, |
50 | SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
51 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
de3f7acb | 52 | #if ASIX_SIGMA_WITH_TRIGGER |
3ba56876 | 53 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, |
54 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
de3f7acb | 55 | #endif |
3ba56876 | 56 | }; |
57 | ||
2d8a5089 GS |
58 | static const char *ext_clock_edges[] = { |
59 | [SIGMA_CLOCK_EDGE_RISING] = "rising", | |
60 | [SIGMA_CLOCK_EDGE_FALLING] = "falling", | |
61 | [SIGMA_CLOCK_EDGE_EITHER] = "either", | |
62 | }; | |
63 | ||
eac48b34 | 64 | #if ASIX_SIGMA_WITH_TRIGGER |
3ba56876 | 65 | static const int32_t trigger_matches[] = { |
66 | SR_TRIGGER_ZERO, | |
67 | SR_TRIGGER_ONE, | |
68 | SR_TRIGGER_RISING, | |
69 | SR_TRIGGER_FALLING, | |
70 | }; | |
eac48b34 | 71 | #endif |
3ba56876 | 72 | |
3553451f | 73 | static void clear_helper(struct dev_context *devc) |
53279f13 | 74 | { |
7fe1f91f | 75 | (void)sigma_force_close(devc); |
53279f13 UH |
76 | } |
77 | ||
3ba56876 | 78 | static int dev_clear(const struct sr_dev_driver *di) |
79 | { | |
9b4d261f GS |
80 | return std_dev_clear_with_callback(di, |
81 | (std_dev_clear_callback)clear_helper); | |
3ba56876 | 82 | } |
83 | ||
53a939ab | 84 | static gboolean bus_addr_in_devices(int bus, int addr, GSList *devs) |
3ba56876 | 85 | { |
53a939ab | 86 | struct sr_usb_dev_inst *usb; |
3ba56876 | 87 | |
53a939ab GS |
88 | for (/* EMPTY */; devs; devs = devs->next) { |
89 | usb = devs->data; | |
90 | if (usb->bus == bus && usb->address == addr) | |
91 | return TRUE; | |
92 | } | |
3ba56876 | 93 | |
53a939ab GS |
94 | return FALSE; |
95 | } | |
3ba56876 | 96 | |
53a939ab GS |
97 | static gboolean known_vid_pid(const struct libusb_device_descriptor *des) |
98 | { | |
9b4d261f GS |
99 | gboolean is_sigma, is_omega; |
100 | ||
53a939ab GS |
101 | if (des->idVendor != USB_VENDOR_ASIX) |
102 | return FALSE; | |
9b4d261f GS |
103 | is_sigma = des->idProduct == USB_PRODUCT_SIGMA; |
104 | is_omega = des->idProduct == USB_PRODUCT_OMEGA; | |
105 | if (!is_sigma && !is_omega) | |
53a939ab GS |
106 | return FALSE; |
107 | return TRUE; | |
108 | } | |
3ba56876 | 109 | |
53a939ab GS |
110 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
111 | { | |
112 | struct drv_context *drvc; | |
113 | libusb_context *usbctx; | |
114 | const char *conn; | |
115 | GSList *l, *conn_devices; | |
116 | struct sr_config *src; | |
117 | GSList *devices; | |
118 | libusb_device **devlist, *devitem; | |
119 | int bus, addr; | |
120 | struct libusb_device_descriptor des; | |
121 | struct libusb_device_handle *hdl; | |
122 | int ret; | |
123 | char conn_id[20]; | |
124 | char serno_txt[16]; | |
125 | char *end; | |
126 | long serno_num, serno_pre; | |
127 | enum asix_device_type dev_type; | |
128 | const char *dev_text; | |
129 | struct sr_dev_inst *sdi; | |
130 | struct dev_context *devc; | |
131 | size_t devidx, chidx; | |
132 | ||
133 | drvc = di->context; | |
134 | usbctx = drvc->sr_ctx->libusb_ctx; | |
135 | ||
136 | /* Find all devices which match an (optional) conn= spec. */ | |
137 | conn = NULL; | |
138 | for (l = options; l; l = l->next) { | |
139 | src = l->data; | |
140 | switch (src->key) { | |
141 | case SR_CONF_CONN: | |
142 | conn = g_variant_get_string(src->data, NULL); | |
143 | break; | |
144 | } | |
3ba56876 | 145 | } |
53a939ab GS |
146 | conn_devices = NULL; |
147 | if (conn) | |
148 | conn_devices = sr_usb_find(usbctx, conn); | |
149 | if (conn && !conn_devices) | |
150 | return NULL; | |
151 | ||
152 | /* Find all ASIX logic analyzers (which match the connection spec). */ | |
153 | devices = NULL; | |
154 | libusb_get_device_list(usbctx, &devlist); | |
155 | for (devidx = 0; devlist[devidx]; devidx++) { | |
156 | devitem = devlist[devidx]; | |
157 | ||
158 | /* Check for connection match if a user spec was given. */ | |
159 | bus = libusb_get_bus_number(devitem); | |
160 | addr = libusb_get_device_address(devitem); | |
161 | if (conn && !bus_addr_in_devices(bus, addr, conn_devices)) | |
162 | continue; | |
163 | snprintf(conn_id, sizeof(conn_id), "%d.%d", bus, addr); | |
164 | ||
165 | /* | |
166 | * Check for known VID:PID pairs. Get the serial number, | |
167 | * to then derive the device type from it. | |
168 | */ | |
169 | libusb_get_device_descriptor(devitem, &des); | |
170 | if (!known_vid_pid(&des)) | |
171 | continue; | |
172 | if (!des.iSerialNumber) { | |
173 | sr_warn("Cannot get serial number (index 0)."); | |
174 | continue; | |
175 | } | |
176 | ret = libusb_open(devitem, &hdl); | |
177 | if (ret < 0) { | |
178 | sr_warn("Cannot open USB device %04x.%04x: %s.", | |
179 | des.idVendor, des.idProduct, | |
180 | libusb_error_name(ret)); | |
181 | continue; | |
182 | } | |
183 | ret = libusb_get_string_descriptor_ascii(hdl, | |
184 | des.iSerialNumber, | |
185 | (unsigned char *)serno_txt, sizeof(serno_txt)); | |
186 | if (ret < 0) { | |
187 | sr_warn("Cannot get serial number (%s).", | |
188 | libusb_error_name(ret)); | |
189 | libusb_close(hdl); | |
190 | continue; | |
191 | } | |
192 | libusb_close(hdl); | |
193 | ||
194 | /* | |
195 | * All ASIX logic analyzers have a serial number, which | |
196 | * reads as a hex number, and tells the device type. | |
197 | */ | |
198 | ret = sr_atol_base(serno_txt, &serno_num, &end, 16); | |
199 | if (ret != SR_OK || !end || *end) { | |
200 | sr_warn("Cannot interpret serial number %s.", serno_txt); | |
201 | continue; | |
202 | } | |
203 | dev_type = ASIX_TYPE_NONE; | |
204 | dev_text = NULL; | |
205 | serno_pre = serno_num >> 16; | |
206 | switch (serno_pre) { | |
207 | case 0xa601: | |
208 | dev_type = ASIX_TYPE_SIGMA; | |
209 | dev_text = "SIGMA"; | |
210 | sr_info("Found SIGMA, serno %s.", serno_txt); | |
211 | break; | |
212 | case 0xa602: | |
213 | dev_type = ASIX_TYPE_SIGMA; | |
214 | dev_text = "SIGMA2"; | |
215 | sr_info("Found SIGMA2, serno %s.", serno_txt); | |
216 | break; | |
217 | case 0xa603: | |
218 | dev_type = ASIX_TYPE_OMEGA; | |
219 | dev_text = "OMEGA"; | |
220 | sr_info("Found OMEGA, serno %s.", serno_txt); | |
221 | if (!ASIX_WITH_OMEGA) { | |
222 | sr_warn("OMEGA support is not implemented yet."); | |
223 | continue; | |
224 | } | |
225 | break; | |
226 | default: | |
227 | sr_warn("Unknown serno %s, skipping.", serno_txt); | |
228 | continue; | |
229 | } | |
230 | ||
231 | /* Create a device instance, add it to the result set. */ | |
232 | ||
233 | sdi = g_malloc0(sizeof(*sdi)); | |
234 | devices = g_slist_append(devices, sdi); | |
235 | sdi->status = SR_ST_INITIALIZING; | |
236 | sdi->vendor = g_strdup("ASIX"); | |
237 | sdi->model = g_strdup(dev_text); | |
238 | sdi->serial_num = g_strdup(serno_txt); | |
239 | sdi->connection_id = g_strdup(conn_id); | |
240 | for (chidx = 0; chidx < ARRAY_SIZE(channel_names); chidx++) | |
241 | sr_channel_new(sdi, chidx, SR_CHANNEL_LOGIC, | |
242 | TRUE, channel_names[chidx]); | |
243 | ||
244 | devc = g_malloc0(sizeof(*devc)); | |
245 | sdi->priv = devc; | |
246 | devc->id.vid = des.idVendor; | |
247 | devc->id.pid = des.idProduct; | |
248 | devc->id.serno = serno_num; | |
249 | devc->id.prefix = serno_pre; | |
250 | devc->id.type = dev_type; | |
5e78a564 | 251 | sr_sw_limits_init(&devc->cfg_limits); |
53a939ab GS |
252 | devc->capture_ratio = 50; |
253 | devc->use_triggers = 0; | |
7fe1f91f GS |
254 | |
255 | /* TODO Retrieve some of this state from hardware? */ | |
256 | devc->firmware_idx = SIGMA_FW_NONE; | |
2d8a5089 | 257 | devc->clock.samplerate = sigma_get_samplerate(sdi); |
3ba56876 | 258 | } |
53a939ab GS |
259 | libusb_free_device_list(devlist, 1); |
260 | g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free); | |
3ba56876 | 261 | |
53a939ab | 262 | return std_scan_complete(di, devices); |
3ba56876 | 263 | } |
264 | ||
3ba56876 | 265 | static int dev_open(struct sr_dev_inst *sdi) |
266 | { | |
267 | struct dev_context *devc; | |
3ba56876 | 268 | |
269 | devc = sdi->priv; | |
270 | ||
53a939ab GS |
271 | if (devc->id.type == ASIX_TYPE_OMEGA && !ASIX_WITH_OMEGA) { |
272 | sr_err("OMEGA support is not implemented yet."); | |
273 | return SR_ERR_NA; | |
274 | } | |
3ba56876 | 275 | |
7fe1f91f | 276 | return sigma_force_open(sdi); |
3ba56876 | 277 | } |
278 | ||
279 | static int dev_close(struct sr_dev_inst *sdi) | |
280 | { | |
281 | struct dev_context *devc; | |
282 | ||
283 | devc = sdi->priv; | |
284 | ||
7fe1f91f | 285 | return sigma_force_close(devc); |
3ba56876 | 286 | } |
287 | ||
dd7a72ea UH |
288 | static int config_get(uint32_t key, GVariant **data, |
289 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 290 | { |
291 | struct dev_context *devc; | |
2d8a5089 | 292 | const char *clock_text; |
3ba56876 | 293 | |
294 | (void)cg; | |
295 | ||
296 | if (!sdi) | |
297 | return SR_ERR; | |
298 | devc = sdi->priv; | |
299 | ||
300 | switch (key) { | |
53a939ab GS |
301 | case SR_CONF_CONN: |
302 | *data = g_variant_new_string(sdi->connection_id); | |
303 | break; | |
3ba56876 | 304 | case SR_CONF_SAMPLERATE: |
2d8a5089 GS |
305 | *data = g_variant_new_uint64(devc->clock.samplerate); |
306 | break; | |
307 | case SR_CONF_EXTERNAL_CLOCK: | |
308 | *data = g_variant_new_boolean(devc->clock.use_ext_clock); | |
309 | break; | |
310 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
311 | clock_text = channel_names[devc->clock.clock_pin]; | |
312 | *data = g_variant_new_string(clock_text); | |
313 | break; | |
314 | case SR_CONF_CLOCK_EDGE: | |
315 | clock_text = ext_clock_edges[devc->clock.clock_edge]; | |
316 | *data = g_variant_new_string(clock_text); | |
3ba56876 | 317 | break; |
318 | case SR_CONF_LIMIT_MSEC: | |
2f7e529c | 319 | case SR_CONF_LIMIT_SAMPLES: |
5e78a564 | 320 | return sr_sw_limits_config_get(&devc->cfg_limits, key, data); |
de3f7acb | 321 | #if ASIX_SIGMA_WITH_TRIGGER |
3ba56876 | 322 | case SR_CONF_CAPTURE_RATIO: |
323 | *data = g_variant_new_uint64(devc->capture_ratio); | |
324 | break; | |
de3f7acb | 325 | #endif |
3ba56876 | 326 | default: |
327 | return SR_ERR_NA; | |
328 | } | |
329 | ||
330 | return SR_OK; | |
331 | } | |
332 | ||
dd7a72ea UH |
333 | static int config_set(uint32_t key, GVariant *data, |
334 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 335 | { |
336 | struct dev_context *devc; | |
5e78a564 GS |
337 | int ret; |
338 | uint64_t want_rate, have_rate; | |
2d8a5089 | 339 | int idx; |
3ba56876 | 340 | |
341 | (void)cg; | |
342 | ||
3ba56876 | 343 | devc = sdi->priv; |
344 | ||
3ba56876 | 345 | switch (key) { |
346 | case SR_CONF_SAMPLERATE: | |
5e78a564 GS |
347 | want_rate = g_variant_get_uint64(data); |
348 | ret = sigma_normalize_samplerate(want_rate, &have_rate); | |
349 | if (ret != SR_OK) | |
350 | return ret; | |
351 | if (have_rate != want_rate) { | |
352 | char *text_want, *text_have; | |
353 | text_want = sr_samplerate_string(want_rate); | |
354 | text_have = sr_samplerate_string(have_rate); | |
355 | sr_info("Adjusted samplerate %s to %s.", | |
356 | text_want, text_have); | |
357 | g_free(text_want); | |
358 | g_free(text_have); | |
359 | } | |
2d8a5089 GS |
360 | devc->clock.samplerate = have_rate; |
361 | break; | |
362 | case SR_CONF_EXTERNAL_CLOCK: | |
363 | devc->clock.use_ext_clock = g_variant_get_boolean(data); | |
364 | break; | |
365 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
366 | idx = std_str_idx(data, ARRAY_AND_SIZE(channel_names)); | |
367 | if (idx < 0) | |
368 | return SR_ERR_ARG; | |
369 | devc->clock.clock_pin = idx; | |
370 | break; | |
371 | case SR_CONF_CLOCK_EDGE: | |
372 | idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges)); | |
373 | if (idx < 0) | |
374 | return SR_ERR_ARG; | |
375 | devc->clock.clock_edge = idx; | |
3ba56876 | 376 | break; |
5e78a564 | 377 | case SR_CONF_LIMIT_MSEC: |
3ba56876 | 378 | case SR_CONF_LIMIT_SAMPLES: |
5e78a564 | 379 | return sr_sw_limits_config_set(&devc->cfg_limits, key, data); |
de3f7acb | 380 | #if ASIX_SIGMA_WITH_TRIGGER |
3ba56876 | 381 | case SR_CONF_CAPTURE_RATIO: |
efad7ccc | 382 | devc->capture_ratio = g_variant_get_uint64(data); |
3ba56876 | 383 | break; |
de3f7acb | 384 | #endif |
3ba56876 | 385 | default: |
758906aa | 386 | return SR_ERR_NA; |
3ba56876 | 387 | } |
388 | ||
758906aa | 389 | return SR_OK; |
3ba56876 | 390 | } |
391 | ||
dd7a72ea UH |
392 | static int config_list(uint32_t key, GVariant **data, |
393 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 394 | { |
3ba56876 | 395 | switch (key) { |
53a939ab | 396 | case SR_CONF_SCAN_OPTIONS: |
3ba56876 | 397 | case SR_CONF_DEVICE_OPTIONS: |
53a939ab GS |
398 | if (cg) |
399 | return SR_ERR_NA; | |
9b4d261f GS |
400 | return STD_CONFIG_LIST(key, data, sdi, cg, |
401 | scanopts, drvopts, devopts); | |
3ba56876 | 402 | case SR_CONF_SAMPLERATE: |
abcd4771 | 403 | *data = sigma_get_samplerates_list(); |
3ba56876 | 404 | break; |
2d8a5089 GS |
405 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: |
406 | *data = g_variant_new_strv(ARRAY_AND_SIZE(channel_names)); | |
407 | break; | |
408 | case SR_CONF_CLOCK_EDGE: | |
409 | *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges)); | |
410 | break; | |
de3f7acb | 411 | #if ASIX_SIGMA_WITH_TRIGGER |
3ba56876 | 412 | case SR_CONF_TRIGGER_MATCH: |
53012da6 | 413 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); |
3ba56876 | 414 | break; |
de3f7acb | 415 | #endif |
3ba56876 | 416 | default: |
417 | return SR_ERR_NA; | |
418 | } | |
419 | ||
420 | return SR_OK; | |
421 | } | |
422 | ||
695dc859 | 423 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
3ba56876 | 424 | { |
425 | struct dev_context *devc; | |
419f1095 GS |
426 | uint16_t pindis_mask; |
427 | uint8_t async, div; | |
8256ed15 | 428 | int triggerpin, ret; |
419f1095 | 429 | uint8_t trigsel2; |
3ba56876 | 430 | struct triggerinout triggerinout_conf; |
431 | struct triggerlut lut; | |
a53b8e4d GS |
432 | uint8_t regval, trgconf_bytes[2], clock_bytes[4], *wrptr; |
433 | size_t count; | |
3ba56876 | 434 | |
3ba56876 | 435 | devc = sdi->priv; |
436 | ||
5e78a564 GS |
437 | /* |
438 | * Setup the device's samplerate from the value which up to now | |
439 | * just got checked and stored. As a byproduct this can pick and | |
440 | * send firmware to the device, reduce the number of available | |
441 | * logic channels, etc. | |
442 | * | |
443 | * Determine an acquisition timeout from optionally configured | |
444 | * sample count or time limits. Which depends on the samplerate. | |
2d8a5089 | 445 | * Force 50MHz samplerate when external clock is in use. |
5e78a564 | 446 | */ |
2d8a5089 GS |
447 | if (devc->clock.use_ext_clock) { |
448 | if (devc->clock.samplerate != SR_MHZ(50)) | |
449 | sr_info("External clock, forcing 50MHz samplerate."); | |
450 | devc->clock.samplerate = SR_MHZ(50); | |
451 | } | |
5e78a564 GS |
452 | ret = sigma_set_samplerate(sdi); |
453 | if (ret != SR_OK) | |
454 | return ret; | |
455 | ret = sigma_set_acquire_timeout(devc); | |
456 | if (ret != SR_OK) | |
457 | return ret; | |
458 | ||
88a5f9ea GS |
459 | ret = sigma_convert_trigger(sdi); |
460 | if (ret != SR_OK) { | |
461 | sr_err("Could not configure triggers."); | |
462 | return ret; | |
3ba56876 | 463 | } |
464 | ||
3ba56876 | 465 | /* Enter trigger programming mode. */ |
0f017b7d GS |
466 | trigsel2 = TRGSEL2_RESET; |
467 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); | |
88a5f9ea GS |
468 | if (ret != SR_OK) |
469 | return ret; | |
3ba56876 | 470 | |
419f1095 | 471 | trigsel2 = 0; |
2d8a5089 | 472 | if (devc->clock.samplerate >= SR_MHZ(100)) { |
f06fb3e9 | 473 | /* 100 and 200 MHz mode. */ |
419f1095 | 474 | /* TODO Decipher the 0x81 magic number's purpose. */ |
88a5f9ea GS |
475 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81); |
476 | if (ret != SR_OK) | |
477 | return ret; | |
3ba56876 | 478 | |
479 | /* Find which pin to trigger on from mask. */ | |
9b4d261f GS |
480 | for (triggerpin = 0; triggerpin < 8; triggerpin++) { |
481 | if (devc->trigger.risingmask & (1 << triggerpin)) | |
482 | break; | |
483 | if (devc->trigger.fallingmask & (1 << triggerpin)) | |
3ba56876 | 484 | break; |
9b4d261f | 485 | } |
3ba56876 | 486 | |
487 | /* Set trigger pin and light LED on trigger. */ | |
419f1095 GS |
488 | trigsel2 = triggerpin & TRGSEL2_PINS_MASK; |
489 | trigsel2 |= TRGSEL2_LEDSEL1; | |
3ba56876 | 490 | |
491 | /* Default rising edge. */ | |
419f1095 | 492 | /* TODO Documentation disagrees, bit set means _rising_ edge. */ |
3ba56876 | 493 | if (devc->trigger.fallingmask) |
419f1095 | 494 | trigsel2 |= TRGSEL2_PINPOL_RISE; |
3ba56876 | 495 | |
2d8a5089 | 496 | } else if (devc->clock.samplerate <= SR_MHZ(50)) { |
419f1095 GS |
497 | /* 50MHz firmware modes. */ |
498 | ||
499 | /* Translate application specs to hardware perspective. */ | |
88a5f9ea GS |
500 | ret = sigma_build_basic_trigger(devc, &lut); |
501 | if (ret != SR_OK) | |
502 | return ret; | |
3ba56876 | 503 | |
419f1095 | 504 | /* Communicate resulting register values to the device. */ |
88a5f9ea GS |
505 | ret = sigma_write_trigger_lut(devc, &lut); |
506 | if (ret != SR_OK) | |
507 | return ret; | |
3ba56876 | 508 | |
419f1095 | 509 | trigsel2 = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0; |
3ba56876 | 510 | } |
511 | ||
512 | /* Setup trigger in and out pins to default values. */ | |
5c231fc4 | 513 | memset(&triggerinout_conf, 0, sizeof(triggerinout_conf)); |
3ba56876 | 514 | triggerinout_conf.trgout_bytrigger = 1; |
515 | triggerinout_conf.trgout_enable = 1; | |
a53b8e4d GS |
516 | /* TODO |
517 | * Verify the correctness of this implementation. The previous | |
518 | * version used to assign to a C language struct with bit fields | |
519 | * which is highly non-portable and hard to guess the resulting | |
520 | * raw memory layout or wire transfer content. The C struct's | |
521 | * field names did not match the vendor documentation's names. | |
522 | * Which means that I could not verify "on paper" either. Let's | |
523 | * re-visit this code later during research for trigger support. | |
524 | */ | |
525 | wrptr = trgconf_bytes; | |
526 | regval = 0; | |
527 | if (triggerinout_conf.trgout_bytrigger) | |
528 | regval |= TRGOPT_TRGOOUTEN; | |
529 | write_u8_inc(&wrptr, regval); | |
530 | regval &= ~TRGOPT_CLEAR_MASK; | |
531 | if (triggerinout_conf.trgout_enable) | |
532 | regval |= TRGOPT_TRGOEN; | |
533 | write_u8_inc(&wrptr, regval); | |
534 | count = wrptr - trgconf_bytes; | |
88a5f9ea GS |
535 | ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION, |
536 | trgconf_bytes, count); | |
537 | if (ret != SR_OK) | |
538 | return ret; | |
a53b8e4d GS |
539 | |
540 | /* Leave trigger programming mode. */ | |
419f1095 | 541 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); |
88a5f9ea GS |
542 | if (ret != SR_OK) |
543 | return ret; | |
3ba56876 | 544 | |
419f1095 GS |
545 | /* |
546 | * Samplerate dependent clock and channels configuration. Some | |
547 | * channels by design are not available at higher clock rates. | |
548 | * Register layout differs between firmware variants (depth 1 | |
549 | * with LSB channel mask above 50MHz, depth 4 with more details | |
550 | * up to 50MHz). | |
551 | * | |
552 | * Derive a mask where bits are set for unavailable channels. | |
553 | * Either send the single byte, or the full byte sequence. | |
554 | */ | |
555 | pindis_mask = ~((1UL << devc->num_channels) - 1); | |
2d8a5089 | 556 | if (devc->clock.samplerate > SR_MHZ(50)) { |
419f1095 GS |
557 | ret = sigma_set_register(devc, WRITE_CLOCK_SELECT, |
558 | pindis_mask & 0xff); | |
8256ed15 | 559 | } else { |
419f1095 GS |
560 | wrptr = clock_bytes; |
561 | /* Select 50MHz base clock, and divider. */ | |
562 | async = 0; | |
2d8a5089 GS |
563 | div = SR_MHZ(50) / devc->clock.samplerate - 1; |
564 | if (devc->clock.use_ext_clock) { | |
565 | async = CLKSEL_CLKSEL8; | |
566 | div = devc->clock.clock_pin + 1; | |
567 | switch (devc->clock.clock_edge) { | |
568 | case SIGMA_CLOCK_EDGE_RISING: | |
569 | div |= CLKSEL_RISING; | |
570 | break; | |
571 | case SIGMA_CLOCK_EDGE_FALLING: | |
572 | div |= CLKSEL_FALLING; | |
573 | break; | |
574 | case SIGMA_CLOCK_EDGE_EITHER: | |
575 | div |= CLKSEL_RISING; | |
576 | div |= CLKSEL_FALLING; | |
577 | break; | |
578 | } | |
579 | } | |
419f1095 GS |
580 | write_u8_inc(&wrptr, async); |
581 | write_u8_inc(&wrptr, div); | |
582 | write_u16be_inc(&wrptr, pindis_mask); | |
583 | ret = sigma_write_register(devc, WRITE_CLOCK_SELECT, | |
584 | clock_bytes, wrptr - clock_bytes); | |
3ba56876 | 585 | } |
88a5f9ea GS |
586 | if (ret != SR_OK) |
587 | return ret; | |
3ba56876 | 588 | |
589 | /* Setup maximum post trigger time. */ | |
88a5f9ea | 590 | ret = sigma_set_register(devc, WRITE_POST_TRIGGER, |
9b4d261f | 591 | (devc->capture_ratio * 255) / 100); |
88a5f9ea GS |
592 | if (ret != SR_OK) |
593 | return ret; | |
3ba56876 | 594 | |
595 | /* Start acqusition. */ | |
9b4d261f | 596 | regval = WMR_TRGRES | WMR_SDRAMWRITEEN; |
22f64ed8 GS |
597 | #if ASIX_SIGMA_WITH_TRIGGER |
598 | regval |= WMR_TRGEN; | |
599 | #endif | |
88a5f9ea GS |
600 | ret = sigma_set_register(devc, WRITE_MODE, regval); |
601 | if (ret != SR_OK) | |
602 | return ret; | |
3ba56876 | 603 | |
88a5f9ea GS |
604 | ret = std_session_send_df_header(sdi); |
605 | if (ret != SR_OK) | |
606 | return ret; | |
3ba56876 | 607 | |
608 | /* Add capture source. */ | |
88a5f9ea | 609 | ret = sr_session_source_add(sdi->session, -1, 0, 10, |
9b4d261f | 610 | sigma_receive_data, (void *)sdi); |
88a5f9ea GS |
611 | if (ret != SR_OK) |
612 | return ret; | |
3ba56876 | 613 | |
614 | devc->state.state = SIGMA_CAPTURE; | |
615 | ||
616 | return SR_OK; | |
617 | } | |
618 | ||
695dc859 | 619 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
3ba56876 | 620 | { |
621 | struct dev_context *devc; | |
622 | ||
3ba56876 | 623 | devc = sdi->priv; |
3ba56876 | 624 | |
dde0175d GS |
625 | /* |
626 | * When acquisition is currently running, keep the receive | |
627 | * routine registered and have it stop the acquisition upon the | |
628 | * next invocation. Else unregister the receive routine here | |
629 | * already. The detour is required to have sample data retrieved | |
630 | * for forced acquisition stops. | |
631 | */ | |
632 | if (devc->state.state == SIGMA_CAPTURE) { | |
633 | devc->state.state = SIGMA_STOPPING; | |
634 | } else { | |
635 | devc->state.state = SIGMA_IDLE; | |
88a5f9ea | 636 | (void)sr_session_source_remove(sdi->session, -1); |
dde0175d | 637 | } |
3ba56876 | 638 | |
639 | return SR_OK; | |
640 | } | |
641 | ||
dd5c48a6 | 642 | static struct sr_dev_driver asix_sigma_driver_info = { |
3ba56876 | 643 | .name = "asix-sigma", |
644 | .longname = "ASIX SIGMA/SIGMA2", | |
645 | .api_version = 1, | |
c2fdcc25 | 646 | .init = std_init, |
700d6b64 | 647 | .cleanup = std_cleanup, |
3ba56876 | 648 | .scan = scan, |
c01bf34c | 649 | .dev_list = std_dev_list, |
3ba56876 | 650 | .dev_clear = dev_clear, |
651 | .config_get = config_get, | |
652 | .config_set = config_set, | |
653 | .config_list = config_list, | |
654 | .dev_open = dev_open, | |
655 | .dev_close = dev_close, | |
656 | .dev_acquisition_start = dev_acquisition_start, | |
657 | .dev_acquisition_stop = dev_acquisition_stop, | |
658 | .context = NULL, | |
659 | }; | |
dd5c48a6 | 660 | SR_REGISTER_DEV_DRIVER(asix_sigma_driver_info); |