build: Set CXXFLAGS when building Python module

[libsigrok.git] / src / hardware / sysclk-lwla / protocol.c

diff --git a/src/hardware/sysclk-lwla/protocol.c b/src/hardware/sysclk-lwla/protocol.c
index ff61a8b3574d786dd8d61c2d6b48c8ae26a45a4a..ba676f69a72c7804bfc6aed3b2bdcca359ce1fa8 100644 (file)
--- a/src/hardware/sysclk-lwla/protocol.c
+++ b/src/hardware/sysclk-lwla/protocol.c
@@ -257,10 +257,10 @@ static void issue_read_start(const struct sr_dev_inst *sdi)
        regvals[0].reg = REG_DIV_BYPASS;
        regvals[0].val = 1;
 
-       regvals[1].reg = REG_MEM_CTRL2;
-       regvals[1].val = 2;
+       regvals[1].reg = REG_MEM_CTRL;
+       regvals[1].val = MEM_CTRL_CLR_IDX;
 
-       regvals[2].reg = REG_MEM_CTRL4;
+       regvals[2].reg = REG_MEM_START;
        regvals[2].val = 4;
 
        devc->reg_write_pos = 0;
@@ -328,7 +328,7 @@ static void issue_stop_capture(const struct sr_dev_inst *sdi)
        regvals = devc->reg_write_seq;
 
        regvals[0].reg = REG_LONG_ADDR;
-       regvals[0].val = 10;
+       regvals[0].val = LREG_CAP_CTRL;
 
        regvals[1].reg = REG_LONG_LOW;
        regvals[1].val = 0;
@@ -372,13 +372,10 @@ static void process_capture_status(const struct sr_dev_inst *sdi)
                return;
        }
 
-       /* TODO: Find out the actual bit width of these fields as stored
-        * in the FPGA.  These fields are definitely less than 64 bit wide
-        * internally, and the unused bits occasionally even contain garbage.
-        */
        mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
-       duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
-       flags    = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
+       duration = LWLA_TO_UINT32(acq->xfer_buf_in[4])
+               | ((uint64_t)LWLA_TO_UINT32(acq->xfer_buf_in[5]) << 32);
+       flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
 
        /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
         * However, the time base used for the duration is apparently not
@@ -713,17 +710,17 @@ SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
        if (ret != SR_OK)
                return ret;
 
-       ret = lwla_read_long_reg(sdi->conn, 100, &value);
+       ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
        if (ret != SR_OK)
                return ret;
 
        /* Ignore the value returned by the first read */
-       ret = lwla_read_long_reg(sdi->conn, 100, &value);
+       ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
        if (ret != SR_OK)
                return ret;
 
        if (value != UINT64_C(0x1234567887654321)) {
-               sr_err("Received invalid test word 0x%16" PRIX64 ".", value);
+               sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
                return SR_ERR;
        }
        return SR_OK;
@@ -814,18 +811,18 @@ SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
                        sr_info("External clock, rising edge.");
        }
 
-       regvals[0].reg = REG_MEM_CTRL2;
-       regvals[0].val = 2;
+       regvals[0].reg = REG_MEM_CTRL;
+       regvals[0].val = MEM_CTRL_CLR_IDX;
 
-       regvals[1].reg = REG_MEM_CTRL2;
-       regvals[1].val = 1;
+       regvals[1].reg = REG_MEM_CTRL;
+       regvals[1].val = MEM_CTRL_WRITE;
 
        regvals[2].reg = REG_LONG_ADDR;
-       regvals[2].val = 10;
+       regvals[2].val = LREG_CAP_CTRL;
 
        regvals[3].reg = REG_LONG_LOW;
-       regvals[3].val = 0x74;
-
+       regvals[3].val = CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO
+                      | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER;
        regvals[4].reg = REG_LONG_HIGH;
        regvals[4].val = 0;
 
@@ -875,10 +872,10 @@ SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
        regvals = devc->reg_write_seq;
 
        regvals[0].reg = REG_LONG_ADDR;
-       regvals[0].val = 10;
+       regvals[0].val = LREG_CAP_CTRL;
 
        regvals[1].reg = REG_LONG_LOW;
-       regvals[1].val = 1;
+       regvals[1].val = CAP_CTRL_TRG_EN;
 
        regvals[2].reg = REG_LONG_HIGH;
        regvals[2].val = 0;