regvals = devc->reg_write_seq;
regvals[0].reg = REG_LONG_ADDR;
- regvals[0].val = 10;
+ regvals[0].val = LREG_CAP_CTRL;
regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 0;
return;
}
- /* TODO: Find out the actual bit width of these fields as stored
- * in the FPGA. These fields are definitely less than 64 bit wide
- * internally, and the unused bits occasionally even contain garbage.
- */
mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
- duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
- flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
+ duration = LWLA_TO_UINT32(acq->xfer_buf_in[4])
+ | ((uint64_t)LWLA_TO_UINT32(acq->xfer_buf_in[5]) << 32);
+ flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
/* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
* However, the time base used for the duration is apparently not
if (ret != SR_OK)
return ret;
- ret = lwla_read_long_reg(sdi->conn, 100, &value);
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
/* Ignore the value returned by the first read */
- ret = lwla_read_long_reg(sdi->conn, 100, &value);
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
regvals[1].val = MEM_CTRL_WRITE;
regvals[2].reg = REG_LONG_ADDR;
- regvals[2].val = 10;
+ regvals[2].val = LREG_CAP_CTRL;
regvals[3].reg = REG_LONG_LOW;
- regvals[3].val = 0x74;
-
+ regvals[3].val = CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO
+ | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER;
regvals[4].reg = REG_LONG_HIGH;
regvals[4].val = 0;
regvals = devc->reg_write_seq;
regvals[0].reg = REG_LONG_ADDR;
- regvals[0].val = 10;
+ regvals[0].val = LREG_CAP_CTRL;
regvals[1].reg = REG_LONG_LOW;
- regvals[1].val = 1;
+ regvals[1].val = CAP_CTRL_TRG_EN;
regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;