Build: Include <config.h> first in all source files

[libsigrok.git] / src / hardware / saleae-logic16 / protocol.c

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index 7e4cb919c496f5ad16ee51ae5c8bf765a1e04c83..af0eed6a37695f577408e204ab89849fee7ae124 100644 (file)
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -19,6 +19,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <config.h>
 #include <stdint.h>
 #include <string.h>
 #include <glib.h>
@@ -26,7 +27,7 @@
 #include <stdio.h>
 #include <errno.h>
 #include <math.h>
-#include "libsigrok.h"
+#include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 #include "protocol.h"
 
@@ -214,7 +215,7 @@ static int do_ep1_command(const struct sr_dev_inst *sdi,
        }
        if (xfer != cmd_len) {
                sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
-                      "%d != %d.", xfer, cmd_len);
+                      "%d != %d.", command[0], xfer, cmd_len);
                return SR_ERR;
        }
 
@@ -230,7 +231,7 @@ static int do_ep1_command(const struct sr_dev_inst *sdi,
        }
        if (xfer != reply_len) {
                sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
-                      "incorrect length %d != %d.", xfer, reply_len);
+                      "incorrect length %d != %d.", command[0], xfer, reply_len);
                return SR_ERR;
        }
 
@@ -363,10 +364,13 @@ static int setup_register_mapping(const struct sr_dev_inst *sdi)
                if ((ret = read_fpga_register(sdi, 7 /* No mapping */, &reg7)) != SR_OK)
                        return ret;
 
-               if (reg0 == 0 && reg7 > 0x10)
+               if (reg0 == 0 && reg7 > 0x10) {
+                       sr_info("Original Saleae Logic16 using new bitstream.");
                        devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
-               else
+               } else {
+                       sr_info("Original Saleae Logic16 using old bitstream.");
                        devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
+               }
        }
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
@@ -488,7 +492,7 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
                sr_info("Uploading FPGA bitstream at %s.", filename);
                if (!(fw = g_fopen(filename, "rb"))) {
                        sr_err("Unable to open bitstream file %s for reading: %s.",
-                              filename, strerror(errno));
+                              filename, g_strerror(errno));
                        return SR_ERR;
                }