* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "protocol.h"
-
#include <stdint.h>
#include <string.h>
#include <glib.h>
#include <math.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"
+#include "protocol.h"
#define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
#define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
usb = sdi->conn;
if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
- command == NULL || (reply_len > 0 && reply == NULL))
+ !command || (reply_len > 0 && !reply))
return SR_ERR_ARG;
encrypt(buf, command, cmd_len);
uint8_t chunk, command[64];
int ret;
- if (cnt < 1 || cnt + offset > 64 || table == NULL)
+ if (cnt < 1 || cnt + offset > 64 || !table)
return SR_ERR_ARG;
while (cnt > 0) {
if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK)
return ret;
- if (version != 0x10) {
- sr_err("Invalid FPGA bitstream version: 0x%02x != 0x10.", version);
+ if (version != 0x10 && version != 0x40 && version != 0x41) {
+ sr_err("Unsupported FPGA version: 0x%02x.", version);
return SR_ERR;
}
if (devc->cur_voltage_range == vrange)
return SR_OK;
- switch (vrange) {
- case VOLTAGE_RANGE_18_33_V:
- filename = FPGA_FIRMWARE_18;
- break;
- case VOLTAGE_RANGE_5_V:
- filename = FPGA_FIRMWARE_33;
- break;
- default:
- sr_err("Unsupported voltage range.");
- return SR_ERR;
- }
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
+ switch (vrange) {
+ case VOLTAGE_RANGE_18_33_V:
+ filename = FPGA_FIRMWARE_18;
+ break;
+ case VOLTAGE_RANGE_5_V:
+ filename = FPGA_FIRMWARE_33;
+ break;
+ default:
+ sr_err("Unsupported voltage range.");
+ return SR_ERR;
+ }
- sr_info("Uploading FPGA bitstream at %s.", filename);
- if ((fw = g_fopen(filename, "rb")) == NULL) {
- sr_err("Unable to open bitstream file %s for reading: %s.",
- filename, strerror(errno));
- return SR_ERR;
- }
+ sr_info("Uploading FPGA bitstream at %s.", filename);
+ if (!(fw = g_fopen(filename, "rb"))) {
+ sr_err("Unable to open bitstream file %s for reading: %s.",
+ filename, strerror(errno));
+ return SR_ERR;
+ }
- buf[0] = COMMAND_FPGA_UPLOAD_INIT;
- if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
- fclose(fw);
- return ret;
- }
+ buf[0] = COMMAND_FPGA_UPLOAD_INIT;
+ if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
+ fclose(fw);
+ return ret;
+ }
- while (1) {
- chunksize = fread(buf, 1, sizeof(buf), fw);
- if (chunksize == 0)
- break;
+ while (1) {
+ chunksize = fread(buf, 1, sizeof(buf), fw);
+ if (chunksize == 0)
+ break;
- for (offset = 0; offset < chunksize; offset += 62) {
- len = (offset + 62 > chunksize ?
- chunksize - offset : 62);
- command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
- command[1] = len;
- memcpy(command + 2, buf + offset, len);
- ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
- if (ret != SR_OK) {
- fclose(fw);
- return ret;
+ for (offset = 0; offset < chunksize; offset += 62) {
+ len = (offset + 62 > chunksize ?
+ chunksize - offset : 62);
+ command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
+ command[1] = len;
+ memcpy(command + 2, buf + offset, len);
+ ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
+ if (ret != SR_OK) {
+ fclose(fw);
+ return ret;
+ }
}
- }
- sr_info("Uploaded %d bytes.", chunksize);
+ sr_info("Uploaded %d bytes.", chunksize);
+ }
+ fclose(fw);
+ sr_info("FPGA bitstream upload done.");
}
- fclose(fw);
- sr_info("FPGA bitstream upload done.");
if ((ret = prime_fpga(sdi)) != SR_OK)
return ret;
if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
return ret;
- if (reg1 != 0x08) {
- sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
- return SR_ERR;
+ /* Ignore FIFO overflow on previous capture */
+ reg1 &= ~0x20;
+
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
+ sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08. "
+ "Proceeding anyway.", reg1);
}
if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
return ret;
- if (reg1 != 0x48) {
- sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1);
- return SR_ERR;
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
+ sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
+ "Proceeding anyway.", reg1);
}
if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
return ret;
- if (reg10 != clock_select) {
- sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.",
- reg10, clock_select);
- return SR_ERR;
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
+ sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
+ "Proceeding anyway.", reg10, clock_select);
}
return SR_OK;
};
int ret;
uint8_t reg1, reg8, reg9;
+ struct dev_context *devc;
+
+ devc = sdi->priv;
if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
return ret;
if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
return ret;
- if (reg1 != 0x08) {
- sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1);
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && (reg1 & ~0x20) != 0x08) {
+ sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20);
return SR_ERR;
}
if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
return ret;
+ if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 & 0x20) {
+ sr_warn("FIFO overflow, capture data may be truncated.");
+ return SR_ERR;
+ }
+
return SR_OK;
}
SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
{
+ uint8_t version;
struct dev_context *devc;
int ret;
if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
return ret;
+ /* mcupro Saleae16 has firmware pre-stored in FPGA.
+ So, we can query it right away. */
+ if (read_fpga_register(sdi, 0, &version) == SR_OK &&
+ (version == 0x40 || version == 0x41)) {
+ sr_info("mcupro Saleae16 detected.");
+ devc->fpga_variant = FPGA_VARIANT_MCUPRO;
+ } else {
+ sr_info("Original Saleae Logic16 detected.");
+ devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
+ }
+
ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
if (ret != SR_OK)
return ret;
return ret;
}
-SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
+SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer)
{
gboolean packet_has_error = FALSE;
struct sr_datafeed_packet packet;
struct dev_context *devc;
size_t new_samples, num_samples;
int trigger_offset;
+ int pre_trigger_samples;
sdi = transfer->user_data;
devc = sdi->priv;
return;
}
- sr_info("receive_transfer(): status %d received %d bytes.",
- transfer->status, transfer->actual_length);
+ sr_info("receive_transfer(): status %s received %d bytes.",
+ libusb_error_name(transfer->status), transfer->actual_length);
switch (transfer->status) {
case LIBUSB_TRANSFER_NO_DEVICE:
devc->sent_samples += new_samples;
} else {
trigger_offset = soft_trigger_logic_check(devc->stl,
- devc->convbuffer, new_samples * 2);
+ devc->convbuffer, new_samples * 2, &pre_trigger_samples);
if (trigger_offset > -1) {
+ devc->sent_samples += pre_trigger_samples;
packet.type = SR_DF_LOGIC;
packet.payload = &logic;
num_samples = new_samples - trigger_offset;
projects / libsigrok.git / blobdiff