#define UC_FIRMWARE "kingst-la-%04x.fw"
#define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream"
#define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream"
+#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream"
+#define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream"
-#define MAX_SAMPLE_RATE SR_MHZ(200)
+#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
+#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
#define MAX_SAMPLE_DEPTH 10e9
#define MAX_PWM_FREQ SR_MHZ(20)
-#define PWM_CLOCK SR_MHZ(200)
+#define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */
/* usb vendor class control requests to the cypress FX2 microcontroller */
-#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
-#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
-#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
-#define CMD_FPGA_ENABLE 0x10
-#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
-#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
-#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
+#define CMD_FPGA_ENABLE 0x10
+#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
+#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
+#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
+#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
+#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
+#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
/*
* fpga spi register addresses for control request CMD_FPGA_SPI:
* as appropriate. In this driver code just use IN transactions
* to read, OUT to write.
*/
-#define REG_RUN 0x00 /* read capture status, write capture start */
-#define REG_PWM_EN 0x02 /* user pwm channels on/off */
-#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
-#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
-#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
-#define REG_TRIGGER 0x20 /* write level and edge trigger config */
-#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
-#define REG_PWM1 0x70 /* write config for user pwm1 */
-#define REG_PWM2 0x78 /* write config for user pwm2 */
+#define REG_RUN 0x00 /* read capture status, write capture start */
+#define REG_PWM_EN 0x02 /* user pwm channels on/off */
+#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
+#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
+#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
+#define REG_TRIGGER 0x20 /* write level and edge trigger config */
+#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
+#define REG_PWM1 0x70 /* write config for user pwm1 */
+#define REG_PWM2 0x78 /* write config for user pwm2 */
static int ctrl_in(const struct sr_dev_inst *sdi,
uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
devc->capture_ratio = 5; /* percent */
devc->cur_channels = 0xffff;
devc->limit_samples = 5000000;
- devc->cur_samplerate = 200000000;
+ devc->cur_samplerate = SR_MHZ(100);
ret = set_threshold_voltage(sdi, devc->threshold_voltage);
if (ret)
devc = sdi->priv;
total = 128 * 1024 * 1024;
- if (devc->cur_samplerate > MAX_SAMPLE_RATE) {
+ if (devc->cur_samplerate > devc->max_samplerate) {
sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
return SR_ERR;
}
- clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
+ clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate;
if (clock_divisor > 0xffff)
clock_divisor = 0xffff;
divisor = (uint16_t)(clock_divisor + 0.5);
- devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
+ devc->cur_samplerate = devc->max_samplerate / divisor;
if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
write_u32le_inc(&wrptr, devc->limit_samples);
write_u8_inc(&wrptr, 0);
write_u32le_inc(&wrptr, devc->pre_trigger_size);
- write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 );
+ write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00);
write_u16le_inc(&wrptr, divisor);
write_u8_inc(&wrptr, 0);
static uint16_t run_state(const struct sr_dev_inst *sdi)
{
uint16_t state;
- static uint16_t previous_state=0;
+ static uint16_t previous_state = 0;
int ret;
if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
* just print a log message if status has changed.
*/
- if(state != previous_state) {
+ if (state != previous_state) {
previous_state = state;
- if((state & 0x0003)==1) {
+ if ((state & 0x0003) == 0x01) {
sr_dbg("run_state: 0x%04x (%s)", state, "idle");
}
- else if((state & 0x000f)==2) {
+ else if ((state & 0x000f) == 0x02) {
sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling");
}
- else if((state & 0x000f)==0x0a) {
+ else if ((state & 0x000f) == 0x0a) {
sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger");
}
- else if((state & 0x000f)==0x0e) {
+ else if ((state & 0x000f) == 0x0e) {
sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling");
}
else {
}
to_read = devc->n_bytes_to_read;
- if (to_read > LA2016_BULK_MAX)
- to_read = LA2016_BULK_MAX;
-
+ /* choose a buffer size for all of the usb transfers */
+ if (to_read >= LA2016_USB_BUFSZ)
+ to_read = LA2016_USB_BUFSZ; /* multiple transfers */
+ else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */
+ to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
buffer = g_try_malloc(to_read);
if (!buffer) {
sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
{
+ struct dev_context *devc;
uint16_t state;
uint8_t buf[8];
int16_t purchase_date_bcd[2];
uint8_t magic;
int ret;
+ devc = sdi->priv;
+
/* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit
* complemented checksum; e.g. 2004DFFB = 2020-April.
* This helps to identify the age of devices if unknown magic numbers occur.
}
else {
sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff);
- if( purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1]) ) {
+ if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) {
sr_err("purchase date: checksum failure");
}
}
switch (magic) {
case 2:
ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016);
+ devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
+ break;
+ case 3:
+ ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016);
+ devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
break;
case 8:
ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A);
+ devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
+ break;
+ case 9:
+ ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A);
+ devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
break;
default:
- sr_err("device_type: device not supported; magic number indicates this is not an LA2016");
+ sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016");
return SR_ERR;
}
projects / libsigrok.git / blobdiff