#define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
/*
- * List of supported devices and their features. See @ref kingst_model
+ * List of known devices and their features. See @ref kingst_model
* for the fields' type and meaning. Table is sorted by EEPROM magic.
+ * More specific items need to go first (additional byte[2/6]). Not
+ * all devices are covered by this driver implementation, but telling
+ * users what was detected is considered useful.
*
- * TODO
- * - Below LA1016 properties were guessed, need verification.
- * - Add LA5016 and LA5032 devices when their EEPROM magic is known.
- * - Does LA1010 fit the driver implementation? Samplerates vary with
- * channel counts, lack of local sample memory. Most probably not.
+ * TODO Verify the identification of models that were not tested before.
*/
static const struct kingst_model models[] = {
- { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, },
- { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, },
- { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, },
- { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, },
+ { 0x02, 0x01, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x02, 0x00, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, },
+ { 0x03, 0x01, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x03, 0x00, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, },
+ { 0x04, 0x00, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x05, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x06, 0x00, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), },
+ { 0x07, 0x00, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x08, 0x00, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x09, 0x00, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x0a, 0x00, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x0b, 0x10, "LA2016", "la2016a2", SR_MHZ(200), 16, 1, 0, },
+ { 0x0c, 0x10, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x0c, 0x00, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x41, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
};
/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
static int set_sample_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ uint64_t baseclock;
uint64_t min_samplerate, eff_samplerate;
uint64_t stream_bandwidth;
uint16_t divider_u16;
devc = sdi->priv;
+ /*
+ * The base clock need not be identical to the maximum samplerate,
+ * and differs between models. The 500MHz devices even use a base
+ * clock of 800MHz, and communicate divider 1 to the hardware to
+ * configure the 500MHz samplerate. This allows them to operate at
+ * a 200MHz samplerate which uses divider 4.
+ */
if (devc->samplerate > devc->model->samplerate) {
sr_err("Too high a sample rate: %" PRIu64 ".",
devc->samplerate);
return SR_ERR_ARG;
}
- min_samplerate = devc->model->samplerate;
+ baseclock = devc->model->baseclock;
+ if (!baseclock)
+ baseclock = devc->model->samplerate;
+ min_samplerate = baseclock;
min_samplerate /= 65536;
if (devc->samplerate < min_samplerate) {
sr_err("Too low a sample rate: %" PRIu64 ".",
devc->samplerate);
return SR_ERR_ARG;
}
- divider_u16 = devc->model->samplerate / devc->samplerate;
- eff_samplerate = devc->model->samplerate / divider_u16;
+ divider_u16 = baseclock / devc->samplerate;
+ eff_samplerate = baseclock / divider_u16;
+ if (eff_samplerate > devc->model->samplerate)
+ eff_samplerate = devc->model->samplerate;
ret = sr_sw_limits_get_remain(&devc->sw_limits,
&limit_samples, NULL, NULL, NULL);
devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
- devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
+ devc->n_bytes_to_read *= devc->transfer_size;
devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
}
/*
- * A chunk (received via USB) contains a number of transfers (USB length
- * divided by 16) which contain a number of packets (5 per transfer) which
- * contain a number of samples (8bit repeat count per 16bit sample data).
+ * A chunk of sample memory was received via USB. These chunks contain
+ * transfers of 16 or 32 bytes each (model dependent size and layout).
+ * Transfers contain a number of packets (5 or 6 per transfer), which
+ * contain a number of samples (16 or 32 sampled pin values, and an
+ * 8bit repeat count for these sampled pin values). A sequence number
+ * follows the packets within the transfer, allows to detect missing or
+ * out of order reception.
+ *
+ * Memory layout for 16-channel models:
+ * - 16 bytes per transfer
+ * - 5x (u16 pins, and u8 count)
+ * - 1x u8 sequence number
+ *
+ * Memory layout for 32-channel models:
+ * - 32 bytes per transfer
+ * - 6x (u32 pins, and u8 count)
+ * - 2x u8 sequence number (inverted, and normal)
+ *
+ * This implementation silently ignores the (weak) sequence number.
*/
static void send_chunk(struct sr_dev_inst *sdi,
const uint8_t *data_buffer, size_t data_length)
{
struct dev_context *devc;
- size_t num_xfers, num_pkts;
+ size_t num_xfers, num_pkts, num_seqs;
const uint8_t *rp;
uint32_t sample_value;
size_t repetitions;
/* Process the received chunk of capture data. */
sample_value = 0;
rp = data_buffer;
- num_xfers = data_length / TRANSFER_PACKET_LENGTH;
+ num_xfers = data_length / devc->transfer_size;
while (num_xfers--) {
num_pkts = devc->packets_per_chunk;
while (num_pkts--) {
- /* TODO Verify 32channel layout. */
if (devc->model->channel_count == 32)
sample_value = read_u32le_inc(&rp);
else if (devc->model->channel_count == 16)
devc->total_samples += repetitions;
write_u32le(sample_buff, sample_value);
- feed_queue_logic_submit(devc->feed_queue,
+ feed_queue_logic_submit_one(devc->feed_queue,
sample_buff, repetitions);
sr_sw_limits_update_samples_read(&devc->sw_limits,
repetitions);
}
}
}
- (void)read_u8_inc(&rp); /* Skip sequence number. */
+ /* Skip the sequence number bytes. */
+ num_seqs = devc->sequence_size;
+ while (num_seqs--)
+ (void)read_u8_inc(&rp);
}
/*
* above). In streaming mode data is not compressed, and memory cells
* neither contain raw sampled pin values at a given point in time. The
* memory content needs transformation.
- * - The memory content can be seen as a sequence of memory cells.
- * - Each cell contains samples that correspond to the same channel.
- * The next cell contains samples for the next channel, etc.
- * - Only enabled channels occupy memory cells. Disabled channels are
- * not part of the capture data memory layout.
- * - The LSB bit position in a cell is the sample which was taken first
- * for this channel. Upper bit positions were taken later.
+ *
+ * All enabled channels get iterated over. Disabled channels will not
+ * occupy space in the streamed sample data. Per channel chunk there is
+ * one 16bit entity which carries samples that were taken at different
+ * times. The least significant bit was sampled first, higher bits were
+ * sampled later. After all 16bit entities for all enabled channels
+ * were seen, the first enabled channel's next chunk follows.
*
* Implementor's note: This routine is inspired by convert_sample_data()
* in the https://github.com/AlexUg/sigrok implementation. Which in turn
* appears to have been derived from the saleae-logic16 sigrok driver.
* The code is phrased conservatively to verify the layout as discussed
* above, performance was not a priority. Operation was verified with an
- * LA2016 device. The memory layout of 32 channel models is yet to get
- * determined.
+ * LA2016 device. The LA5032 reportedly shares the 16 samples per channel
+ * layout, just round-robins through a potentially larger set of enabled
+ * channels before returning to the first of the channels.
*/
static void stream_data(struct sr_dev_inst *sdi,
const uint8_t *data_buffer, size_t data_length)
/* TODO Add soft trigger support when in stream mode? */
- /*
- * TODO Are memory cells always as wide as the channel count?
- * Are they always 16bits wide? Verify for 32 channel devices.
- */
- bit_count = devc->model->channel_count;
- if (bit_count == 32) {
- data_length /= sizeof(uint32_t);
- } else if (bit_count == 16) {
- data_length /= sizeof(uint16_t);
- } else {
- /*
- * Unhandled case. Acquisition should not start.
- * The statement silences the compiler.
- */
- return;
- }
+ /* All channels' chunks carry 16 samples for one channel. */
+ bit_count = 16;
+ data_length /= sizeof(uint16_t);
+
rp = data_buffer;
sample_value = 0;
while (data_length--) {
/* Get another entity. */
- if (bit_count == 32)
- sample_value = read_u32le_inc(&rp);
- else if (bit_count == 16)
- sample_value = read_u16le_inc(&rp);
+ sample_value = read_u16le_inc(&rp);
/* Map the entity's bits to a channel's samples. */
ch_mask = stream->channel_masks[stream->channel_index];
for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
sample_value = stream->sample_data[bit_idx];
write_u32le(sample_buff, sample_value);
- feed_queue_logic_submit(devc->feed_queue, sample_buff, 1);
+ feed_queue_logic_submit_one(devc->feed_queue,
+ sample_buff, 1);
}
sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count);
devc->total_samples += bit_count;
const uint8_t *rdptr;
uint8_t date_yy, date_mm;
uint8_t dinv_yy, dinv_mm;
- uint8_t magic;
+ uint8_t magic, magic2;
size_t model_idx;
const struct kingst_model *model;
int ret;
sr_spew("EEPROM magic bytes %s.", txt->str);
sr_hexdump_free(txt);
}
- if ((buf[0] ^ buf[1]) == 0xff) {
- /* Primary copy of magic passes complement check. */
+ magic = 0;
+ magic2 = 0;
+ if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) {
+ /* Primary copy of magic passes complement check (4 bytes). */
magic = buf[0];
- sr_dbg("Using primary magic, value %d.", (int)magic);
+ magic2 = buf[2];
+ sr_dbg("Using primary magic 0x%hhx (0x%hhx).", magic, magic2);
+ } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) {
+ /* Backup copy of magic passes complement check (4 bytes). */
+ magic = buf[4];
+ magic2 = buf[6];
+ sr_dbg("Using secondary magic 0x%hhx (0x%hhx).", magic, magic2);
+ } else if ((buf[0] ^ buf[1]) == 0xff) {
+ /* Primary copy of magic passes complement check (2 bytes). */
+ magic = buf[0];
+ sr_dbg("Using primary magic 0x%hhx.", magic);
} else if ((buf[4] ^ buf[5]) == 0xff) {
- /* Backup copy of magic passes complement check. */
+ /* Backup copy of magic passes complement check (2 bytes). */
magic = buf[4];
- sr_dbg("Using backup magic, value %d.", (int)magic);
+ sr_dbg("Using secondary magic 0x%hhx.", magic);
} else {
sr_err("Cannot find consistent device type identification.");
- magic = 0;
}
devc->identify_magic = magic;
+ devc->identify_magic2 = magic2;
devc->model = NULL;
for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
model = &models[model_idx];
if (model->magic != magic)
continue;
+ if (model->magic2 && model->magic2 != magic2)
+ continue;
devc->model = model;
sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
model->name, model->channel_count,
devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
model->fpga_stem);
sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
+ if (!model->channel_count) {
+ sr_warn("Device lacks logic channels. Not supported.");
+ devc->model = NULL;
+ }
break;
}
if (!devc->model) {
projects / libsigrok.git / blobdiff