#include "libsigrok-internal.h"
#include "protocol.h"
-#define FPGA_FIRMWARE "kingst-la2016a-fpga.bitstream"
#define UC_FIRMWARE "kingst-la-%04x.fw"
+#define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream"
+#define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream"
#define MAX_SAMPLE_RATE SR_MHZ(200)
#define MAX_SAMPLE_DEPTH 10e9
return SR_OK;
}
-static int upload_fpga_bitstream(const struct sr_dev_inst *sdi)
+static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname)
{
struct dev_context *devc;
struct drv_context *drvc;
drvc = sdi->driver->context;
usb = sdi->conn;
- sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE);
+ sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
- ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE);
+ ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname);
if (ret != SR_OK) {
- sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE);
+ sr_err("could not find fpga firmware %s!", bitstream_fname);
return ret;
}
{
struct dev_context *devc;
double clock_divisor;
- uint64_t psa;
uint64_t total;
int ret;
uint16_t divisor;
sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
- psa = devc->pre_trigger_size * 256;
wrptr = buf;
write_u32le_inc(&wrptr, devc->limit_samples);
- write_u48le_inc(&wrptr, psa);
- write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
- write_u16le_inc(&wrptr, clock_divisor);
+ write_u8_inc(&wrptr, 0);
+ write_u32le_inc(&wrptr, devc->pre_trigger_size);
+ write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 );
+ write_u16le_inc(&wrptr, divisor);
+ write_u8_inc(&wrptr, 0);
ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
if (ret != SR_OK) {
return SR_OK;
}
-/**
- * lowest 2 bit are probably:
- * 2: recording
- * 1: finished
- * next 2 bit indicate whether we are still waiting for triggering
- * 0: waiting
- * 3: triggered
+/* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte]
+ * and the bits are interpreted as follows:
+ *
+ * register 0:
+ * bit0 1= idle
+ * bit1 1= writing to sdram
+ * bit2 0= waiting_for_trigger 1=been_triggered
+ * bit3 0= pretrigger_sampling 1=posttrigger_sampling
+ * ...unknown...
+ * register 1:
+ * meaning of bits unknown (but vendor software reads this, so just do the same)
+ *
+ * The run state values occur in this order:
+ * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%)
+ * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously)
+ * 0x85EE: running
+ * 0x85ED: idle
*/
static uint16_t run_state(const struct sr_dev_inst *sdi)
{
uint16_t state;
+ static uint16_t previous_state=0;
int ret;
if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
sr_err("failed to read run state!");
return ret;
}
- sr_dbg("run_state: 0x%04x", state);
+
+ /* This function is called about every 50ms.
+ * To avoid filling the log file with redundant information during long captures,
+ * just print a log message if status has changed.
+ */
+
+ if(state != previous_state) {
+ previous_state = state;
+ if((state & 0x0003)==1) {
+ sr_dbg("run_state: 0x%04x (%s)", state, "idle");
+ }
+ else if((state & 0x000f)==2) {
+ sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling");
+ }
+ else if((state & 0x000f)==0x0a) {
+ sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger");
+ }
+ else if((state & 0x000f)==0x0e) {
+ sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling");
+ }
+ else {
+ sr_dbg("run_state: 0x%04x", state);
+ }
+ }
return state;
}
SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
{
- struct dev_context *devc;
- int ret;
- uint32_t i1;
- uint32_t i2[2];
uint16_t state;
+ uint8_t buf[8];
+ int16_t purchase_date_bcd[2];
+ uint8_t magic;
+ int ret;
- /* this unknown_cmd1 seems to depend on the FPGA bitstream */
- uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf };
- uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd };
- uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea };
- uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f };
- uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)];
- uint8_t *expected_unknown_resp1;
- uint8_t *unknown_cmd1;
-
- uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca };
- uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 };
- uint8_t unknown_resp2[sizeof(expected_unknown_resp2)];
+ /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit
+ * complemented checksum; e.g. 2004DFFB = 2020-April.
+ * This helps to identify the age of devices if unknown magic numbers occur.
+ */
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) {
+ sr_err("failed to read eeprom purchase_date_bcd");
+ }
+ else {
+ sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff);
+ if( purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1]) ) {
+ sr_err("purchase date: checksum failure");
+ }
+ }
- devc = sdi->priv;
+ /*
+ * There are four known kingst logic analyser devices which use this same usb vid and pid:
+ * LA2016, LA1016 and the older revision of each of these. They all use the same hardware
+ * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are
+ * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08.
+ * For example;
+ *
+ * magic=0x08
+ * | ~magic=0xf7
+ * | |
+ * 08F7000008F710EF
+ * | |
+ * | ~magic-backup
+ * magic-backup
+ *
+ * It seems that only these magic bytes are used, other bytes shown above are 'don't care'.
+ * Changing the magic byte on newer device to older magic causes OEM software to load
+ * the older fpga bitstream. The device then functions but has channels out of order.
+ * It's likely the bitstreams were changed to move input channel pins due to PCB changes.
+ *
+ * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
+ * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
+ * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
+ * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
+ *
+ * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing
+ * the vendor software actions, either raising errors or loading specific bitstreams.
+ *
+ * Note:
+ * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream
+ * will not authenticate with ic U10, which has different security coding for each device type.
+ */
- if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
- sr_err("failed to read i1");
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) {
+ sr_err("failed to read eeprom device identifier bytes");
return ret;
}
- sr_dbg("i1: 0x%08x", i1);
- if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
- sr_err("failed to read i2");
- return ret;
+ magic = 0;
+ if (buf[0] == (0x0ff & ~buf[1])) {
+ /* primary copy of magic passes complement check */
+ magic = buf[0];
}
- sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]);
-
- if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) {
- sr_err("failed to upload fpga bitstream");
- return ret;
+ else if (buf[4] == (0x0ff & ~buf[5])) {
+ /* backup copy of magic passes complement check */
+ sr_dbg("device_type: using backup copy of magic number");
+ magic = buf[4];
}
- if (run_state(sdi) == 0xffff) {
- sr_err("run_state after fpga bitstream upload is 0xffff!");
+ sr_dbg("device_type: magic number is %hhu", magic);
+
+ /* select the correct fpga bitstream for this device */
+ switch (magic) {
+ case 2:
+ ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016);
+ break;
+ case 8:
+ ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A);
+ break;
+ default:
+ sr_err("device_type: device not supported; magic number indicates this is not an LA2016");
return SR_ERR;
}
- if (devc->bitstream_size == 0x2b602) {
- // v3.4.0
- unknown_cmd1 = unknown_cmd1_340;
- expected_unknown_resp1 = expected_unknown_resp1_340;
- } else {
- // v3.4.2
- if (devc->bitstream_size != 0x2b839)
- sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size);
- unknown_cmd1 = unknown_cmd1_342;
- expected_unknown_resp1 = expected_unknown_resp1_342;
- }
- if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
- sr_err("failed to send unknown_cmd1");
- return ret;
- }
- g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
- sr_err("failed to read unknown_resp1");
+ if (ret != SR_OK) {
+ sr_err("failed to upload fpga bitstream");
return ret;
}
- if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1)))
- sr_dbg("unknown_cmd1 response is not as expected, this is to be expected...");
state = run_state(sdi);
- if (state != 0x85e9)
+ if (state != 0x85e9) {
sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
-
- if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
- sr_err("failed to send unknown_cmd2");
- return ret;
- }
- g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
- sr_err("failed to read unknown_resp2");
- return ret;
}
- if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
- sr_dbg("unknown_cmd2 response is not as expected!");
if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
- sr_err("failed to send unknown_cmd3");
+ sr_err("failed to send CMD_BULK_RESET");
return ret;
}
+
sr_dbg("device should be initialized");
return set_defaults(sdi);
projects / libsigrok.git / blobdiff