ipdbg-la: revers order of trigger settings

[libsigrok.git] / src / hardware / ipdbg-logic-analyser / api.c

diff --git a/src/hardware/ipdbg-logic-analyser/api.c b/src/hardware/ipdbg-logic-analyser/api.c
index 05469606644f37dcae4754c5ebdbf0e37e902ceb..9c6d7f123e38aa8707a8148b58a7767b65f586fe 100644 (file)
--- a/src/hardware/ipdbg-logic-analyser/api.c
+++ b/src/hardware/ipdbg-logic-analyser/api.c
@@ -126,7 +126,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
     sr_err("limit samples = %d\n", devc->limit_samples_max);
     /////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-    for (int i = 0; i < devc->DATA_WIDTH; i++)
+    for (unsigned int i = 0; i < devc->DATA_WIDTH; i++)
     {
         snprintf(buff, bufSize, "ch%d", i);
         sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, buff);