drivers: Use ARRAY_AND_SIZE where possible.

[libsigrok.git] / src / hardware / dreamsourcelab-dslogic / api.c

diff --git a/src/hardware/dreamsourcelab-dslogic/api.c b/src/hardware/dreamsourcelab-dslogic/api.c
index 08dded0140364826bd61bf73d45b4affc8c06ab9..fe49d5f325f68ac0dec57946165fd539f548bebe 100644 (file)
--- a/src/hardware/dreamsourcelab-dslogic/api.c
+++ b/src/hardware/dreamsourcelab-dslogic/api.c
@@ -67,7 +67,6 @@ static const uint32_t devopts[] = {
        SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 };
 
-/* Names assigned to available edge slope choices. */
 static const char *const signal_edge_names[] = {
        [DS_EDGE_RISING] = "rising",
        [DS_EDGE_FALLING] = "falling",
@@ -223,7 +222,6 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                        }
                }
 
-               /* Skip if the device was not found. */
                if (!prof)
                        continue;
 
@@ -537,8 +535,7 @@ static int config_set(uint32_t key, GVariant *data,
                devc->continuous_mode = g_variant_get_boolean(data);
                break;
        case SR_CONF_CLOCK_EDGE:
-               i = lookup_index(data, signal_edge_names,
-                                  ARRAY_SIZE(signal_edge_names));
+               i = lookup_index(data, ARRAY_AND_SIZE(signal_edge_names));
                if (i < 0)
                        return SR_ERR_ARG;
                devc->clock_edge = i;
@@ -557,7 +554,6 @@ static int config_list(uint32_t key, GVariant **data,
        GVariant *gvar, *range[2];
        GVariantBuilder gvb;
        unsigned int i;
-       double v;
 
        devc = (sdi) ? sdi->priv : NULL;
 
@@ -566,34 +562,24 @@ static int config_list(uint32_t key, GVariant **data,
        case SR_CONF_DEVICE_OPTIONS:
                return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
        case SR_CONF_VOLTAGE_THRESHOLD:
-               g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
                if (!strcmp(devc->profile->model, "DSLogic")) {
+                       g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
                        for (i = 0; i < ARRAY_SIZE(voltage_thresholds); i++) {
                                range[0] = g_variant_new_double(voltage_thresholds[i].low);
                                range[1] = g_variant_new_double(voltage_thresholds[i].high);
                                gvar = g_variant_new_tuple(range, 2);
                                g_variant_builder_add_value(&gvb, gvar);
                        }
+                       *data = g_variant_builder_end(&gvb);
                } else {
-                       for (v = 0.0; v <= 5.0; v += 0.1) {
-                               range[0] = g_variant_new_double(v);
-                               range[1] = g_variant_new_double(v);
-                               gvar = g_variant_new_tuple(range, 2);
-                               g_variant_builder_add_value(&gvb, gvar);
-                       }
+                       *data = std_gvar_min_max_step_thresholds(0.0, 5.0, 0.1);
                }
-               *data = g_variant_builder_end(&gvb);
                break;
        case SR_CONF_SAMPLERATE:
-               g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
-               gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), devc->samplerates,
-                               devc->num_samplerates, sizeof(uint64_t));
-               g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
-               *data = g_variant_builder_end(&gvb);
+               *data = std_gvar_samplerates(devc->samplerates, devc->num_samplerates);
                break;
        case SR_CONF_CLOCK_EDGE:
-               *data = g_variant_new_strv(signal_edge_names,
-                       ARRAY_SIZE(signal_edge_names));
+               *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edge_names));
                break;
        default:
                return SR_ERR_NA;