* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
+ * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
READ_TEST = 15,
};
-#define LEDSEL0 6
-#define LEDSEL1 7
-
-
-#define EVENTS_PER_CLUSTER 7
-
-#define CHUNK_SIZE 1024
+#define TRGSEL2_LEDSEL0 (1 << 6)
+#define TRGSEL2_LEDSEL1 (1 << 7)
/* WRITE_MODE register fields. */
#define WMR_SDRAMWRITEEN (1 << 0)
#define RMR_POSTTRIGGERED (1 << 6)
/* not used: bit position 7 */
+/*
+ * Trigger options. First and second write are similar, but _some_
+ * positions change their meaning.
+ */
+#define TRGOPT_TRGIEN (1 << 7)
+#define TRGOPT_TRGOEN (1 << 6)
+#define TRGOPT_TRGOINEN (1 << 5) /* 1st write */
+#define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */
+#define TRGOPT_TRGOEVNTEN (1 << 4) /* 1st write */
+#define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */
+#define TRGOPT_TRGOOUTEN (1 << 3) /* 1st write */
+#define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */
+#define TRGOPT_TRGOUTR_OUT (1 << 1)
+#define TRGOPT_TRGOUTR_EN (1 << 0)
+#define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN)
+
/*
* Layout of the sample data DRAM, which will be downloaded to the PC:
*
* Sigma memory is organized in 32K rows. Each row contains 64 clusters.
- * Each cluster contains a timestamp (16bit) and 7 samples (16bits each).
- * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit).
+ * Each cluster contains a timestamp (16bit) and 7 events (16bits each).
+ * Events contain 16 bits of sample data (potentially taken at multiple
+ * sample points, see below).
+ *
+ * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The
+ * size of a memory row is 1024 bytes. Assuming x16 organization of the
+ * memory array, address specs (sample count, trigger position) are kept
+ * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit
+ * refer to the "event" within the row. Because there is one timestamp for
+ * seven events each, one memory row can hold up to 64x7 == 448 events.
*
* Sample data is represented in 16bit quantities. The first sample in
* the cluster corresponds to the cluster's timestamp. Each next sample
* one sample period, according to the samplerate). In the absence of
* pin level changes, no data is provided (RLE compression). A cluster
* is enforced for each 64K ticks of the timestamp, to reliably handle
- * rollover and determination of the next timestamp of the next cluster.
+ * rollover and determine the next timestamp of the next cluster.
*
+ * For samplerates up to 50MHz, an event directly translates to one set
+ * of sample data at a single sample point, spanning up to 16 channels.
* For samplerates of 100MHz, there is one 16 bit entity for each 20ns
* period (50MHz rate). The 16 bit memory contains 2 samples of up to
* 8 channels. Bits of multiple samples are interleaved. For samplerates
* of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
* each 5ns apart.
- *
- * Memory addresses (sample count, trigger position) are kept in 24bit
- * entities. The upper 15 bit refer to the "row", the lower 9 bit refer
- * to the "event" within the row. Because there is one timestamp for
- * seven samples each, one memory row can hold up to 64x7 == 448 samples.
*/
-/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
-struct sigma_dram_cluster {
- uint8_t timestamp_lo;
- uint8_t timestamp_hi;
- struct {
- uint8_t sample_hi;
- uint8_t sample_lo;
- } samples[7];
-};
+#define ROW_COUNT 32768
+#define ROW_LENGTH_BYTES 1024
+#define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t))
+#define ROW_SHIFT 9 /* log2 of u16 count */
+#define ROW_MASK ((1UL << ROW_SHIFT) - 1)
+#define EVENTS_PER_CLUSTER 7
+#define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER))
+#define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER)
-/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
struct sigma_dram_line {
- struct sigma_dram_cluster cluster[64];
+ struct sigma_dram_cluster {
+ uint16_t timestamp;
+ uint16_t samples[EVENTS_PER_CLUSTER];
+ } cluster[CLUSTERS_PER_ROW];
};
struct clockselect_50 {
uint8_t async;
- uint8_t fraction;
+ uint64_t fraction;
uint16_t disabled_channels;
};
struct sigma_state {
enum {
SIGMA_UNINITIALIZED = 0,
+ SIGMA_CONFIG,
SIGMA_IDLE,
SIGMA_CAPTURE,
SIGMA_STOPPING,
uint16_t lastsample;
};
+enum sigma_firmware_idx {
+ SIGMA_FW_NONE,
+ SIGMA_FW_50MHZ,
+ SIGMA_FW_100MHZ,
+ SIGMA_FW_200MHZ,
+ SIGMA_FW_SYNC,
+ SIGMA_FW_FREQ,
+};
+
+struct submit_buffer;
+
struct dev_context {
struct {
uint16_t vid, pid;
uint16_t prefix;
enum asix_device_type type;
} id;
- struct ftdi_context ftdic;
- uint64_t cur_samplerate;
- uint64_t limit_msec;
- uint64_t limit_samples;
- uint64_t sent_samples;
- uint64_t start_time;
- int cur_firmware;
+ struct {
+ struct ftdi_context ctx;
+ gboolean is_open, must_close;
+ } ftdi;
+ uint64_t samplerate;
+ struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
+ struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
+ struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */
+ enum sigma_firmware_idx firmware_idx;
int num_channels;
- int cur_channels;
int samples_per_event;
uint64_t capture_ratio;
struct sigma_trigger trigger;
int use_triggers;
struct sigma_state state;
+ struct submit_buffer *buffer;
};
extern SR_PRIV const uint64_t samplerates[];
extern SR_PRIV const size_t samplerates_count;
-SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
- struct dev_context *devc);
-SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc);
-SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc);
-SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
- uint64_t limit_samples);
-SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
+/* "Automatic" and forced USB connection open/close support. */
+SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi);
+SR_PRIV int sigma_check_close(struct dev_context *devc);
+SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi);
+SR_PRIV int sigma_force_close(struct dev_context *devc);
+
+SR_PRIV int sigma_write_register(struct dev_context *devc,
+ uint8_t reg, uint8_t *data, size_t len);
+SR_PRIV int sigma_set_register(struct dev_context *devc,
+ uint8_t reg, uint8_t value);
+SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
+ struct triggerlut *lut);
+SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate);
+SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi);
+SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc);
SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
-SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc);
+SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
+ struct triggerlut *lut);
#endif
projects / libsigrok.git / blobdiff