READ_TEST = 15,
};
+#define HI4(b) (((b) >> 4) & 0x0f)
+#define LO4(b) (((b) >> 0) & 0x0f)
+
+#define BIT_MASK(l) ((1UL << (l)) - 1)
+
+#define CLKSEL_CLKSEL8 (1 << 0)
+#define CLKSEL_PINMASK BIT_MASK(4)
+#define CLKSEL_RISING (1 << 4)
+#define CLKSEL_FALLING (1 << 5)
+
+#define TRGSEL_SELINC_MASK BIT_MASK(2)
+#define TRGSEL_SELINC_SHIFT 0
+#define TRGSEL_SELRES_MASK BIT_MASK(2)
+#define TRGSEL_SELRES_SHIFT 2
+#define TRGSEL_SELA_MASK BIT_MASK(2)
+#define TRGSEL_SELA_SHIFT 4
+#define TRGSEL_SELB_MASK BIT_MASK(2)
+#define TRGSEL_SELB_SHIFT 6
+#define TRGSEL_SELC_MASK BIT_MASK(2)
+#define TRGSEL_SELC_SHIFT 8
+#define TRGSEL_SELPRESC_MASK BIT_MASK(4)
+#define TRGSEL_SELPRESC_SHIFT 12
+
+enum trgsel_selcode_t {
+ TRGSEL_SELCODE_LEVEL = 0,
+ TRGSEL_SELCODE_FALL = 1,
+ TRGSEL_SELCODE_RISE = 2,
+ TRGSEL_SELCODE_EVENT = 3,
+ TRGSEL_SELCODE_NEVER = 3,
+};
+
#define TRGSEL2_PINS_MASK (0x07 << 0)
#define TRGSEL2_PINPOL_RISE (1 << 3)
#define TRGSEL2_LUT_ADDR_MASK (0x0f << 0)
struct triggerlut {
/* The actual LUTs. */
uint16_t m0d[4], m1d[4], m2d[4];
- uint16_t m3, m3s, m4;
+ uint16_t m3q, m3s, m4;
/* Parameters should be sent as a single register write. */
struct {
SIGMA_FW_FREQ,
};
+enum ext_clock_edge_t {
+ SIGMA_CLOCK_EDGE_RISING,
+ SIGMA_CLOCK_EDGE_FALLING,
+ SIGMA_CLOCK_EDGE_EITHER,
+};
+
struct submit_buffer;
struct dev_context {
struct ftdi_context ctx;
gboolean is_open, must_close;
} ftdi;
- uint64_t samplerate;
+ struct {
+ uint64_t samplerate;
+ gboolean use_ext_clock;
+ size_t clock_pin;
+ enum ext_clock_edge_t clock_edge;
+ } clock;
struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */