* few discrete values, while setter routines accept any user specified
* rate that is supported by the hardware.
*/
-SR_PRIV const uint64_t samplerates[] = {
+static const uint64_t samplerates[] = {
/* 50MHz and integer divider. 1/2/5 steps (where possible). */
SR_KHZ(200), SR_KHZ(500),
SR_MHZ(1), SR_MHZ(2), SR_MHZ(5),
SR_MHZ(100), SR_MHZ(200),
};
-SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
+SR_PRIV GVariant *sigma_get_samplerates_list(void)
+{
+ return std_gvar_samplerates(samplerates, ARRAY_SIZE(samplerates));
+}
static const char *firmware_files[] = {
[SIGMA_FW_50MHZ] = "asix-sigma-50.fw", /* 50MHz, 8bit divider. */
* that's a programmer's error and needs adjustment in the complete call
* stack of the respective code path.
*/
+#define SIGMA_MAX_REG_DEPTH 32
+
+/*
+ * Implementor's note: The FPGA command set supports register access
+ * with automatic address adjustment. This operation is documented to
+ * wrap within a 16-address range, it cannot cross boundaries where the
+ * register address' nibble overflows. An internal helper assumes that
+ * callers remain within this auto-adjustment range, and thus multi
+ * register access requests can never exceed that count.
+ */
+#define SIGMA_MAX_REG_COUNT 16
+
SR_PRIV int sigma_write_register(struct dev_context *devc,
uint8_t reg, uint8_t *data, size_t len)
{
- uint8_t buf[80], *wrptr;
+ uint8_t buf[2 + SIGMA_MAX_REG_DEPTH * 2], *wrptr;
size_t idx;
- if (2 + 2 * len > sizeof(buf)) {
+ if (len > SIGMA_MAX_REG_DEPTH) {
sr_err("Short write buffer for %zu bytes to reg %u.", len, reg);
return SR_ERR_BUG;
}
wrptr = buf;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
for (idx = 0; idx < len; idx++) {
- write_u8_inc(&wrptr, REG_DATA_LOW | (data[idx] & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data[idx] >> 4));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data[idx]));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data[idx]));
}
return sigma_write_sr(devc, buf, wrptr - buf);
int ret;
wrptr = buf;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
write_u8_inc(&wrptr, REG_READ_ADDR);
ret = sigma_write_sr(devc, buf, wrptr - buf);
if (ret != SR_OK)
return sigma_read_sr(devc, data, len);
}
+static int sigma_get_register(struct dev_context *devc,
+ uint8_t reg, uint8_t *data)
+{
+ return sigma_read_register(devc, reg, data, sizeof(*data));
+}
+
+static int sigma_get_registers(struct dev_context *devc,
+ uint8_t reg, uint8_t *data, size_t count)
+{
+ uint8_t buf[2 + SIGMA_MAX_REG_COUNT], *wrptr;
+ size_t idx;
+ int ret;
+
+ if (count > SIGMA_MAX_REG_COUNT) {
+ sr_err("Short command buffer for %zu reg reads at %u.", count, reg);
+ return SR_ERR_BUG;
+ }
+
+ wrptr = buf;
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
+ for (idx = 0; idx < count; idx++)
+ write_u8_inc(&wrptr, REG_READ_ADDR | REG_ADDR_INC);
+ ret = sigma_write_sr(devc, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
+
+ return sigma_read_sr(devc, data, count);
+}
+
static int sigma_read_pos(struct dev_context *devc,
uint32_t *stoppos, uint32_t *triggerpos, uint8_t *mode)
{
- /*
- * Read 7 registers starting at trigger position LSB.
- * Which yields two 24bit counter values, and mode flags.
- */
- const uint8_t buf[] = {
- /* Setup first register address. */
- REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
- /* Retrieve trigger position. */
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- /* Retrieve stop position. */
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- /* Retrieve mode register. */
- REG_READ_ADDR | REG_ADDR_INC,
- }, *rdptr;
uint8_t result[7];
+ const uint8_t *rdptr;
uint32_t v32;
uint8_t v8;
int ret;
- ret = sigma_write_sr(devc, buf, sizeof(buf));
- if (ret != SR_OK)
- return ret;
-
- ret = sigma_read_sr(devc, result, sizeof(result));
+ /*
+ * Read 7 registers starting at trigger position LSB.
+ * Which yields two 24bit counter values, and mode flags.
+ */
+ ret = sigma_get_registers(devc, READ_TRIGGER_POS_LOW,
+ result, sizeof(result));
if (ret != SR_OK)
return ret;
static int sigma_read_dram(struct dev_context *devc,
uint16_t startchunk, size_t numchunks, uint8_t *data)
{
- uint8_t buf[128], *wrptr;
+ uint8_t buf[128], *wrptr, regval;
size_t chunk;
int sel, ret;
gboolean is_last;
/* Communicate DRAM start address (memory row, aka samples line). */
wrptr = buf;
- write_u8_inc(&wrptr, startchunk >> 8);
- write_u8_inc(&wrptr, startchunk & 0xff);
+ write_u16be_inc(&wrptr, startchunk);
ret = sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf);
if (ret != SR_OK)
return ret;
for (chunk = 0; chunk < numchunks; chunk++) {
sel = chunk % 2;
is_last = chunk == numchunks - 1;
- if (!is_last)
- write_u8_inc(&wrptr, REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel));
- write_u8_inc(&wrptr, REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel));
+ if (!is_last) {
+ regval = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel);
+ write_u8_inc(&wrptr, regval);
+ }
+ regval = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel);
+ write_u8_inc(&wrptr, regval);
if (!is_last)
write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK);
}
SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
struct triggerlut *lut)
{
- int i;
- uint8_t tmp[2];
+ int lut_addr;
uint16_t bit;
+ uint8_t m3d, m2d, m1d, m0d;
uint8_t buf[6], *wrptr, regval;
int ret;
- /* Transpose the table and send to Sigma. */
- for (i = 0; i < 16; i++) {
- bit = 1 << i;
+ /*
+ * Translate the LUT part of the trigger configuration from the
+ * application's perspective to the hardware register's bitfield
+ * layout. Send the LUT to the device. This configures the logic
+ * which combines pin levels or edges.
+ */
+ for (lut_addr = 0; lut_addr < 16; lut_addr++) {
+ bit = 1 << lut_addr;
- tmp[0] = tmp[1] = 0;
+ /* - M4 M3S M3Q */
+ m3d = 0;
+ if (lut->m4 & bit)
+ m3d |= 1 << 2;
+ if (lut->m3s & bit)
+ m3d |= 1 << 1;
+ if (lut->m3 & bit)
+ m3d |= 1 << 0;
- if (lut->m2d[0] & bit)
- tmp[0] |= 0x01;
- if (lut->m2d[1] & bit)
- tmp[0] |= 0x02;
- if (lut->m2d[2] & bit)
- tmp[0] |= 0x04;
+ /* M2D3 M2D2 M2D1 M2D0 */
+ m2d = 0;
if (lut->m2d[3] & bit)
- tmp[0] |= 0x08;
+ m2d |= 1 << 3;
+ if (lut->m2d[2] & bit)
+ m2d |= 1 << 2;
+ if (lut->m2d[1] & bit)
+ m2d |= 1 << 1;
+ if (lut->m2d[0] & bit)
+ m2d |= 1 << 0;
- if (lut->m3 & bit)
- tmp[0] |= 0x10;
- if (lut->m3s & bit)
- tmp[0] |= 0x20;
- if (lut->m4 & bit)
- tmp[0] |= 0x40;
+ /* M1D3 M1D2 M1D1 M1D0 */
+ m1d = 0;
+ if (lut->m1d[3] & bit)
+ m1d |= 1 << 3;
+ if (lut->m1d[2] & bit)
+ m1d |= 1 << 2;
+ if (lut->m1d[1] & bit)
+ m1d |= 1 << 1;
+ if (lut->m1d[0] & bit)
+ m1d |= 1 << 0;
- if (lut->m0d[0] & bit)
- tmp[1] |= 0x01;
- if (lut->m0d[1] & bit)
- tmp[1] |= 0x02;
- if (lut->m0d[2] & bit)
- tmp[1] |= 0x04;
+ /* M0D3 M0D2 M0D1 M0D0 */
+ m0d = 0;
if (lut->m0d[3] & bit)
- tmp[1] |= 0x08;
-
- if (lut->m1d[0] & bit)
- tmp[1] |= 0x10;
- if (lut->m1d[1] & bit)
- tmp[1] |= 0x20;
- if (lut->m1d[2] & bit)
- tmp[1] |= 0x40;
- if (lut->m1d[3] & bit)
- tmp[1] |= 0x80;
+ m0d |= 1 << 3;
+ if (lut->m0d[2] & bit)
+ m0d |= 1 << 2;
+ if (lut->m0d[1] & bit)
+ m0d |= 1 << 1;
+ if (lut->m0d[0] & bit)
+ m0d |= 1 << 0;
/*
- * This logic seems redundant, but separates the value
- * determination from the wire format, and is useful
- * during future maintenance and research.
+ * Send 16bits with M3D/M2D and M1D/M0D bit masks to the
+ * TriggerSelect register, then strobe the LUT write by
+ * passing A3-A0 to TriggerSelect2. Hold RESET during LUT
+ * programming.
*/
wrptr = buf;
- write_u8_inc(&wrptr, tmp[0]);
- write_u8_inc(&wrptr, tmp[1]);
- ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
+ write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0));
+ write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0));
+ ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT,
+ buf, wrptr - buf);
if (ret != SR_OK)
return ret;
- ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x30 | i);
+ ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2,
+ TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
+ (lut_addr & TRGSEL2_LUT_ADDR_MASK));
if (ret != SR_OK)
return ret;
}
- /* Send the parameters */
+ /*
+ * Send the parameters. This covers counters and durations.
+ */
wrptr = buf;
regval = 0;
- regval |= lut->params.selc << 6;
- regval |= lut->params.selpresc << 0;
+ regval |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT;
+ regval |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT;
write_u8_inc(&wrptr, regval);
regval = 0;
- regval |= lut->params.selinc << 6;
- regval |= lut->params.selres << 4;
- regval |= lut->params.sela << 2;
- regval |= lut->params.selb << 0;
+ regval |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT;
+ regval |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT;
+ regval |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT;
+ regval |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT;
write_u8_inc(&wrptr, regval);
- write_u16le_inc(&wrptr, lut->params.cmpb);
- write_u16le_inc(&wrptr, lut->params.cmpa);
+ write_u16be_inc(&wrptr, lut->params.cmpb);
+ write_u16be_inc(&wrptr, lut->params.cmpa);
ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
if (ret != SR_OK)
return ret;
*/
static int sigma_fpga_init_la(struct dev_context *devc)
{
- uint8_t buf[16], *wrptr;
+ uint8_t buf[20], *wrptr;
uint8_t data_55, data_aa, mode;
uint8_t result[3];
const uint8_t *rdptr;
wrptr = buf;
/* Read ID register. */
- write_u8_inc(&wrptr, REG_ADDR_LOW | (READ_ID & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (READ_ID >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(READ_ID));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(READ_ID));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Write 0x55 to scratch register, read back. */
data_55 = 0x55;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (data_55 & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_55 >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_55));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_55));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Write 0xaa to scratch register, read back. */
data_aa = 0xaa;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (data_aa & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_aa >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_aa));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_aa));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Initiate SDRAM initialization in mode register. */
mode = WMR_SDRAMINIT;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_MODE & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (mode & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (mode >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_MODE));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_MODE));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(mode));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(mode));
/*
* Send the command sequence which contains 3 READ requests.
return SR_ERR_ARG;
}
+SR_PRIV uint64_t sigma_get_samplerate(const struct sr_dev_inst *sdi)
+{
+ /* TODO Retrieve value from hardware. */
+ (void)sdi;
+ return samplerates[0];
+}
+
SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
if (ret != SR_OK)
return ret;
do {
- ret = sigma_read_register(devc, READ_MODE,
- &modestatus, sizeof(modestatus));
+ ret = sigma_get_register(devc, READ_MODE, &modestatus);
if (ret != SR_OK) {
sr_err("Could not poll for post-trigger state.");
return FALSE;
SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
struct triggerlut *lut)
{
- int i,j;
+ int i, j;
uint16_t masks[2];
memset(lut, 0, sizeof(*lut));
projects / libsigrok.git / blobdiff