if (ret < 0) {
sr_err("ftdi_usb_open failed: %s",
ftdi_get_error_string(ftdic));
- return 0;
+ return SR_ERR;
}
ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
ftdi_get_error_string(ftdic));
- return 0;
+ return SR_ERR;
}
/* Four times the speed of sigmalogan - Works well. */
if (ret < 0) {
sr_err("ftdi_set_baudrate failed: %s",
ftdi_get_error_string(ftdic));
- return 0;
+ return SR_ERR;
}
/* Initialize the FPGA for firmware upload. */
struct drv_context *drvc;
size_t i;
int ret;
+ int num_channels;
devc = sdi->priv;
drvc = sdi->driver->context;
* firmware is required and higher rates might limit the set
* of available channels.
*/
+ num_channels = devc->num_channels;
if (samplerate <= SR_MHZ(50)) {
ret = upload_firmware(drvc->sr_ctx, 0, devc);
- devc->num_channels = 16;
+ num_channels = 16;
} else if (samplerate == SR_MHZ(100)) {
ret = upload_firmware(drvc->sr_ctx, 1, devc);
- devc->num_channels = 8;
+ num_channels = 8;
} else if (samplerate == SR_MHZ(200)) {
ret = upload_firmware(drvc->sr_ctx, 2, devc);
- devc->num_channels = 4;
+ num_channels = 4;
}
/*
* an "event" (memory organization internal to the device).
*/
if (ret == SR_OK) {
+ devc->num_channels = num_channels;
devc->cur_samplerate = samplerate;
devc->samples_per_event = 16 / devc->num_channels;
devc->state.state = SIGMA_IDLE;