size_t lut_addr;
uint16_t bit;
uint8_t m3d, m2d, m1d, m0d;
- uint8_t buf[6], *wrptr, v8;
- uint16_t selreg;
+ uint8_t buf[6], *wrptr;
+ uint8_t trgsel2;
+ uint16_t lutreg, selreg;
int ret;
/*
* which combines pin levels or edges.
*/
for (lut_addr = 0; lut_addr < 16; lut_addr++) {
- bit = 1 << lut_addr;
+ bit = BIT(lut_addr);
/* - M4 M3S M3Q */
m3d = 0;
if (lut->m4 & bit)
- m3d |= 1 << 2;
+ m3d |= BIT(2);
if (lut->m3s & bit)
- m3d |= 1 << 1;
+ m3d |= BIT(1);
if (lut->m3q & bit)
- m3d |= 1 << 0;
+ m3d |= BIT(0);
/* M2D3 M2D2 M2D1 M2D0 */
m2d = 0;
if (lut->m2d[3] & bit)
- m2d |= 1 << 3;
+ m2d |= BIT(3);
if (lut->m2d[2] & bit)
- m2d |= 1 << 2;
+ m2d |= BIT(2);
if (lut->m2d[1] & bit)
- m2d |= 1 << 1;
+ m2d |= BIT(1);
if (lut->m2d[0] & bit)
- m2d |= 1 << 0;
+ m2d |= BIT(0);
/* M1D3 M1D2 M1D1 M1D0 */
m1d = 0;
if (lut->m1d[3] & bit)
- m1d |= 1 << 3;
+ m1d |= BIT(3);
if (lut->m1d[2] & bit)
- m1d |= 1 << 2;
+ m1d |= BIT(2);
if (lut->m1d[1] & bit)
- m1d |= 1 << 1;
+ m1d |= BIT(1);
if (lut->m1d[0] & bit)
- m1d |= 1 << 0;
+ m1d |= BIT(0);
/* M0D3 M0D2 M0D1 M0D0 */
m0d = 0;
if (lut->m0d[3] & bit)
- m0d |= 1 << 3;
+ m0d |= BIT(3);
if (lut->m0d[2] & bit)
- m0d |= 1 << 2;
+ m0d |= BIT(2);
if (lut->m0d[1] & bit)
- m0d |= 1 << 1;
+ m0d |= BIT(1);
if (lut->m0d[0] & bit)
- m0d |= 1 << 0;
+ m0d |= BIT(0);
/*
* Send 16bits with M3D/M2D and M1D/M0D bit masks to the
* programming.
*/
wrptr = buf;
- write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0));
- write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0));
+ lutreg = 0;
+ lutreg <<= 4; lutreg |= m3d;
+ lutreg <<= 4; lutreg |= m2d;
+ lutreg <<= 4; lutreg |= m1d;
+ lutreg <<= 4; lutreg |= m0d;
+ write_u16be_inc(&wrptr, lutreg);
ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT,
buf, wrptr - buf);
if (ret != SR_OK)
return ret;
- v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
+ trgsel2 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
(lut_addr & TRGSEL2_LUT_ADDR_MASK);
- ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8);
+ ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trgsel2);
if (ret != SR_OK)
return ret;
}
* mode and sending configuration data. Set D7 and toggle D2, D3, D4
* a few times.
*/
-#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */
-#define BB_PIN_PROG (1 << 1) /* D1, PROG */
-#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */
-#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */
-#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */
-#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */
-#define BB_PIN_DIN (1 << 6) /* D6, DIN */
-#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */
+#define BB_PIN_CCLK BIT(0) /* D0, CCLK */
+#define BB_PIN_PROG BIT(1) /* D1, PROG */
+#define BB_PIN_D2 BIT(2) /* D2, (part of) SUICIDE */
+#define BB_PIN_D3 BIT(3) /* D3, (part of) SUICIDE */
+#define BB_PIN_D4 BIT(4) /* D4, (part of) SUICIDE (unused?) */
+#define BB_PIN_INIT BIT(5) /* D5, INIT, input pin */
+#define BB_PIN_DIN BIT(6) /* D6, DIN */
+#define BB_PIN_D7 BIT(7) /* D7, (part of) SUICIDE */
#define BB_BITRATE (750 * 1000)
#define BB_PINMASK (0xff & ~BB_PIN_INIT)
return SR_OK;
}
- devc->state.state = SIGMA_CONFIG;
+ devc->state = SIGMA_CONFIG;
/* Set the cable to bitbang mode. */
ret = ftdi_set_bitmode(&devc->ftdi.ctx, BB_PINMASK, BITMODE_BITBANG);
}
/* Keep track of successful firmware download completion. */
- devc->state.state = SIGMA_IDLE;
+ devc->state = SIGMA_IDLE;
devc->firmware_idx = firmware_idx;
sr_info("Firmware uploaded.");
uint64_t worst_cluster_time_ms;
uint64_t count_msecs, acquire_msecs;
- sr_sw_limits_init(&devc->acq_limits);
+ sr_sw_limits_init(&devc->limit.acquire);
/* Get sample count limit, convert to msecs. */
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_SAMPLES, &data);
if (ret != SR_OK)
return ret;
count_msecs = 1000 * user_count / devc->clock.samplerate + 1;
/* Get time limit, which is in msecs. */
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_MSEC, &data);
if (ret != SR_OK)
return ret;
worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate;
acquire_msecs += 2 * worst_cluster_time_ms;
data = g_variant_new_uint64(acquire_msecs);
- ret = sr_sw_limits_config_set(&devc->acq_limits,
+ ret = sr_sw_limits_config_set(&devc->limit.acquire,
SR_CONF_LIMIT_MSEC, data);
g_variant_unref(data);
if (ret != SR_OK)
return ret;
- sr_sw_limits_acquisition_start(&devc->acq_limits);
+ sr_sw_limits_acquisition_start(&devc->limit.acquire);
return SR_OK;
}
* firmware is required and higher rates might limit the set
* of available channels.
*/
- num_channels = devc->num_channels;
+ num_channels = devc->interp.num_channels;
if (samplerate <= SR_MHZ(50)) {
ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_50MHZ);
num_channels = 16;
* which the device will communicate within an "event").
*/
if (ret == SR_OK) {
- devc->num_channels = num_channels;
- devc->samples_per_event = 16 / devc->num_channels;
+ devc->interp.num_channels = num_channels;
+ devc->interp.samples_per_event = 16 / devc->interp.num_channels;
}
/*
if (!buffer->sample_data)
return SR_ERR_MALLOC;
buffer->write_pointer = buffer->sample_data;
- sr_sw_limits_init(&devc->feed_limits);
+ sr_sw_limits_init(&devc->limit.submit);
buffer->sdi = sdi;
memset(&buffer->logic, 0, sizeof(buffer->logic));
GVariant *data;
uint64_t total;
- limits = &devc->feed_limits;
+ limits = &devc->limit.submit;
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_SAMPLES, &data);
if (ret != SR_OK)
return ret;
int ret;
buffer = devc->buffer;
- limits = &devc->feed_limits;
+ limits = &devc->limit.submit;
if (sr_sw_limits_check(limits))
count = 0;
return SR_OK;
}
+static int alloc_sample_buffer(struct dev_context *devc)
+{
+ size_t alloc_size;
+
+ devc->interp.fetch.lines_per_read = 32;
+ alloc_size = sizeof(devc->interp.fetch.rcvd_lines[0]);
+ alloc_size *= devc->interp.fetch.lines_per_read;
+ devc->interp.fetch.rcvd_lines = g_try_malloc0(alloc_size);
+ if (!devc->interp.fetch.rcvd_lines)
+ return SR_ERR_MALLOC;
+
+ return SR_OK;
+}
+
+static void free_sample_buffer(struct dev_context *devc)
+{
+ g_free(devc->interp.fetch.rcvd_lines);
+ devc->interp.fetch.rcvd_lines = NULL;
+}
+
/*
* In 100 and 200 MHz mode, only a single pin rising/falling can be
* set as trigger. In other modes, two rising/falling triggers can be set,
/* Ignore disabled channels with a trigger. */
if (!match->channel->enabled)
continue;
- channelbit = 1 << match->channel->index;
+ channelbit = BIT(match->channel->index);
if (devc->clock.samplerate >= SR_MHZ(100)) {
/* Fast trigger support. */
if (trigger_set) {
* One 16bit item contains two samples of 8bits each. The bits of
* multiple samples are interleaved.
*/
-static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
+static uint16_t sigma_deinterlace_data_2x8(uint16_t indata, int idx)
{
uint16_t outdata;
* One 16bit item contains four samples of 4bits each. The bits of
* multiple samples are interleaved.
*/
-static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
+static uint16_t sigma_deinterlace_data_4x4(uint16_t indata, int idx)
{
uint16_t outdata;
struct sigma_dram_cluster *dram_cluster,
size_t events_in_cluster, gboolean triggered)
{
- struct sigma_state *ss;
uint16_t tsdiff, ts, sample, item16;
size_t count;
size_t evt;
* for simple level and edge triggers. It would not for timed or
* counted conditions, which currently are not supported.)
*/
- ss = &devc->state;
ts = sigma_dram_cluster_ts(dram_cluster);
- tsdiff = ts - ss->lastts;
+ tsdiff = ts - devc->interp.last.ts;
if (tsdiff > 0) {
- sample = ss->lastsample;
- count = tsdiff * devc->samples_per_event;
+ sample = devc->interp.last.sample;
+ count = tsdiff * devc->interp.samples_per_event;
(void)check_and_submit_sample(devc, sample, count, FALSE);
}
- ss->lastts = ts + EVENTS_PER_CLUSTER;
+ devc->interp.last.ts = ts + EVENTS_PER_CLUSTER;
/*
* Grab sample data from the current cluster and prepare their
sample = 0;
for (evt = 0; evt < events_in_cluster; evt++) {
item16 = sigma_dram_cluster_data(dram_cluster, evt);
- if (devc->clock.samplerate == SR_MHZ(200)) {
- sample = sigma_deinterlace_200mhz_data(item16, 0);
+ if (devc->interp.samples_per_event == 4) {
+ sample = sigma_deinterlace_data_4x4(item16, 0);
check_and_submit_sample(devc, sample, 1, triggered);
- sample = sigma_deinterlace_200mhz_data(item16, 1);
+ sample = sigma_deinterlace_data_4x4(item16, 1);
check_and_submit_sample(devc, sample, 1, triggered);
- sample = sigma_deinterlace_200mhz_data(item16, 2);
+ sample = sigma_deinterlace_data_4x4(item16, 2);
check_and_submit_sample(devc, sample, 1, triggered);
- sample = sigma_deinterlace_200mhz_data(item16, 3);
+ sample = sigma_deinterlace_data_4x4(item16, 3);
check_and_submit_sample(devc, sample, 1, triggered);
- } else if (devc->clock.samplerate == SR_MHZ(100)) {
- sample = sigma_deinterlace_100mhz_data(item16, 0);
+ } else if (devc->interp.samples_per_event == 2) {
+ sample = sigma_deinterlace_data_2x8(item16, 0);
check_and_submit_sample(devc, sample, 1, triggered);
- sample = sigma_deinterlace_100mhz_data(item16, 1);
+ sample = sigma_deinterlace_data_2x8(item16, 1);
check_and_submit_sample(devc, sample, 1, triggered);
} else {
sample = item16;
check_and_submit_sample(devc, sample, 1, triggered);
}
}
- ss->lastsample = sample;
+ devc->interp.last.sample = sample;
}
/*
static int download_capture(struct sr_dev_inst *sdi)
{
- const uint32_t chunks_per_read = 32;
-
struct dev_context *devc;
- struct sigma_dram_line *dram_line;
+ struct sigma_sample_interp *interp;
uint32_t stoppos, triggerpos;
uint8_t modestatus;
size_t line_idx;
int ret;
devc = sdi->priv;
+ interp = &devc->interp;
sr_info("Downloading sample data.");
- devc->state.state = SIGMA_DOWNLOAD;
+ devc->state = SIGMA_DOWNLOAD;
/*
* Ask the hardware to stop data acquisition. Reception of the
dl_first_line = dl_lines_total + 1;
dl_lines_total = ROW_COUNT - 2;
}
- dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
- if (!dram_line)
+ ret = alloc_sample_buffer(devc);
+ if (ret != SR_OK)
return FALSE;
ret = alloc_submit_buffer(sdi);
if (ret != SR_OK)
return FALSE;
dl_lines_done = 0;
while (dl_lines_total > dl_lines_done) {
- /* We can download only up-to 32 DRAM lines in one go! */
- dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
+ /* Get another set of DRAM lines in one read. */
+ dl_lines_curr = dl_lines_total - dl_lines_done;
+ if (dl_lines_curr > interp->fetch.lines_per_read)
+ dl_lines_curr = interp->fetch.lines_per_read;
dl_line = dl_first_line + dl_lines_done;
dl_line %= ROW_COUNT;
ret = sigma_read_dram(devc, dl_line, dl_lines_curr,
- (uint8_t *)dram_line);
+ (uint8_t *)interp->fetch.rcvd_lines);
if (ret != SR_OK)
return FALSE;
+ interp->fetch.curr_line = &interp->fetch.rcvd_lines[0];
- /* This is the first DRAM line, so find the initial timestamp. */
+ /* Seed initial timestamp from the first DRAM line. */
if (dl_lines_done == 0) {
- devc->state.lastts =
- sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
- devc->state.lastsample = 0;
+ interp->last.ts =
+ sigma_dram_cluster_ts(&interp->fetch.curr_line->cluster[0]);
+ interp->last.sample = 0;
}
for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) {
if (dl_lines_done + line_idx == trg_line)
trigger_event = trg_event;
- decode_chunk_ts(devc, dram_line + line_idx,
+ decode_chunk_ts(devc, interp->fetch.curr_line,
dl_events_in_line, trigger_event);
+ interp->fetch.curr_line++;
}
dl_lines_done += dl_lines_curr;
}
flush_submit_buffer(devc);
free_submit_buffer(devc);
- g_free(dram_line);
+ free_sample_buffer(devc);
std_session_send_df_end(sdi);
- devc->state.state = SIGMA_IDLE;
+ devc->state = SIGMA_IDLE;
sr_dev_acquisition_stop(sdi);
return TRUE;
struct dev_context *devc;
devc = sdi->priv;
- if (sr_sw_limits_check(&devc->acq_limits))
+ if (sr_sw_limits_check(&devc->limit.acquire))
return download_capture(sdi);
return TRUE;
sdi = cb_data;
devc = sdi->priv;
- if (devc->state.state == SIGMA_IDLE)
+ if (devc->state == SIGMA_IDLE)
return TRUE;
/*
* keep checking configured limits which will terminate the
* acquisition and initiate download.
*/
- if (devc->state.state == SIGMA_STOPPING)
+ if (devc->state == SIGMA_STOPPING)
return download_capture(sdi);
- if (devc->state.state == SIGMA_CAPTURE)
+ if (devc->state == SIGMA_CAPTURE)
return sigma_capture_mode(sdi);
return TRUE;
lut_entry[quad] = ~0;
for (bitidx = 0; bitidx < 16; bitidx++) {
for (ch = 0; ch < 4; ch++) {
- quadmask = 1 << ch;
+ quadmask = BIT(ch);
bitmask = quadmask << (quad * 4);
if (!(spec_mask & bitmask))
continue;
bit_idx_low = !(bitidx & quadmask);
if (spec_value_low == bit_idx_low)
continue;
- lut_entry[quad] &= ~(1 << bitidx);
+ lut_entry[quad] &= ~BIT(bitidx);
}
}
}
static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
size_t index, gboolean neg, uint16_t *mask)
{
- size_t i, j;
- int x[2][2], tmp, a, b, aset, bset, rset;
+ int x[2][2], a, b, aset, bset, rset;
+ size_t bitidx;
- memset(x, 0, sizeof(x));
+ /*
+ * Beware! The x, a, b, aset, bset, rset variables strictly
+ * require the limited 0..1 range. They are not interpreted
+ * as logically true, instead bit arith is done on them.
+ */
- /* Trigger detect condition. */
+ /* Construct a pattern which detects the condition. */
+ memset(x, 0, sizeof(x));
switch (oper) {
case OP_LEVEL:
x[0][1] = 1;
break;
}
- /* Transpose if neg is set. */
+ /* Transpose the pattern if the condition is negated. */
if (neg) {
+ size_t i, j;
+ int tmp;
+
for (i = 0; i < 2; i++) {
for (j = 0; j < 2; j++) {
tmp = x[i][j];
}
}
- /* Update mask with function. */
- for (i = 0; i < 16; i++) {
- a = (i >> (2 * index + 0)) & 1;
- b = (i >> (2 * index + 1)) & 1;
+ /* Update the LUT mask with the function's condition. */
+ for (bitidx = 0; bitidx < 16; bitidx++) {
+ a = (bitidx & BIT(2 * index + 0)) ? 1 : 0;
+ b = (bitidx & BIT(2 * index + 1)) ? 1 : 0;
- aset = (*mask >> i) & 1;
+ aset = (*mask & BIT(bitidx)) ? 1 : 0;
bset = x[b][a];
- rset = 0;
if (func == FUNC_AND || func == FUNC_NAND)
rset = aset & bset;
else if (func == FUNC_OR || func == FUNC_NOR)
rset = aset | bset;
else if (func == FUNC_XOR || func == FUNC_NXOR)
rset = aset ^ bset;
+ else
+ rset = 0;
if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
- rset = !rset;
-
- *mask &= ~(1 << i);
+ rset = 1 - rset;
if (rset)
- *mask |= 1 << i;
+ *mask |= BIT(bitidx);
+ else
+ *mask &= ~BIT(bitidx);
}
}
memset(&masks, 0, sizeof(masks));
condidx = 0;
for (bitidx = 0; bitidx < 16; bitidx++) {
- mask = 1 << bitidx;
+ mask = BIT(bitidx);
value = devc->trigger.risingmask | devc->trigger.fallingmask;
if (!(value & mask))
continue;
projects / libsigrok.git / blobdiff