dslogic: Fix incorrect samplerate setting.

[libsigrok.git] / src / hardware / asix-sigma / asix-sigma.c

diff --git a/src/hardware/asix-sigma/asix-sigma.c b/src/hardware/asix-sigma/asix-sigma.c
index 23e388fc3985e0651abd0216cae1e1cacf9789dc..6e7f1fd716d52c04fd8c816348cb3088d2629e97 100644 (file)
--- a/src/hardware/asix-sigma/asix-sigma.c
+++ b/src/hardware/asix-sigma/asix-sigma.c
@@ -130,13 +130,23 @@ static int sigma_write(void *buf, size_t size, struct dev_context *devc)
        return ret;
 }
 
+/*
+ * NOTE: We chose the buffer size to be large enough to hold any write to the
+ * device. We still print a message just in case.
+ */
 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
                                struct dev_context *devc)
 {
        size_t i;
-       uint8_t buf[len + 2];
+       uint8_t buf[80];
        int idx = 0;
 
+       if ((len + 2) > sizeof(buf)) {
+               sr_err("Attempted to write %zu bytes, but buffer is too small.",
+                      len + 2);
+               return SR_ERR_BUG;
+       }
+
        buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
        buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
 
@@ -419,7 +429,7 @@ static int sigma_fpga_init_bitbang(struct dev_context *devc)
                0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
                0x01, 0x01,
        };
-       int i, ret, timeout = 10000;
+       int i, ret, timeout = (10 * 1000);
        uint8_t data;
 
        /* Section 2. part 1), do the FPGA suicide. */
@@ -441,7 +451,7 @@ static int sigma_fpga_init_bitbang(struct dev_context *devc)
                if (data & (1 << 5))
                        return 0;
                /* The D6 was not asserted yet, wait a bit. */
-               g_usleep(10000);
+               g_usleep(10 * 1000);
        }
 
        return SR_ERR_TIMEOUT;
@@ -590,7 +600,7 @@ static int upload_firmware(int firmware_idx, struct dev_context *devc)
        }
 
        /* Four times the speed of sigmalogan - Works well. */
-       ret = ftdi_set_baudrate(ftdic, 750000);
+       ret = ftdi_set_baudrate(ftdic, 750 * 1000);
        if (ret < 0) {
                sr_err("ftdi_set_baudrate failed: %s",
                       ftdi_get_error_string(ftdic));