#include "protocol.h"
/*
- * Channel numbers seem to go from 1-16, according to this image:
- * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
- * (the cable has two additional GND pins, and a TI and TO pin)
+ * Channels are labelled 1-16, see this vendor's image of the cable:
+ * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg (TI/TO are
+ * additional trigger in/out signals).
*/
static const char *channel_names[] = {
"1", "2", "3", "4", "5", "6", "7", "8",
SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
SR_CONF_CONN | SR_CONF_GET,
SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
-#if ASIX_SIGMA_WITH_TRIGGER
+ SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
-#endif
};
-#if ASIX_SIGMA_WITH_TRIGGER
+static const char *ext_clock_edges[] = {
+ [SIGMA_CLOCK_EDGE_RISING] = "rising",
+ [SIGMA_CLOCK_EDGE_FALLING] = "falling",
+ [SIGMA_CLOCK_EDGE_EITHER] = "either",
+};
+
static const int32_t trigger_matches[] = {
SR_TRIGGER_ZERO,
SR_TRIGGER_ONE,
SR_TRIGGER_RISING,
SR_TRIGGER_FALLING,
};
-#endif
static void clear_helper(struct dev_context *devc)
{
devc->id.serno = serno_num;
devc->id.prefix = serno_pre;
devc->id.type = dev_type;
- sr_sw_limits_init(&devc->cfg_limits);
+ sr_sw_limits_init(&devc->limit.config);
devc->capture_ratio = 50;
- devc->use_triggers = 0;
+ devc->use_triggers = FALSE;
- /* TODO Retrieve some of this state from hardware? */
- devc->firmware_idx = SIGMA_FW_NONE;
- devc->samplerate = sigma_get_samplerate(sdi);
+ /* Get current hardware configuration (or use defaults). */
+ (void)sigma_fetch_hw_config(sdi);
}
libusb_free_device_list(devlist, 1);
g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
+ const char *clock_text;
(void)cg;
*data = g_variant_new_string(sdi->connection_id);
break;
case SR_CONF_SAMPLERATE:
- *data = g_variant_new_uint64(devc->samplerate);
+ *data = g_variant_new_uint64(devc->clock.samplerate);
+ break;
+ case SR_CONF_EXTERNAL_CLOCK:
+ *data = g_variant_new_boolean(devc->clock.use_ext_clock);
+ break;
+ case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+ clock_text = channel_names[devc->clock.clock_pin];
+ *data = g_variant_new_string(clock_text);
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ clock_text = ext_clock_edges[devc->clock.clock_edge];
+ *data = g_variant_new_string(clock_text);
break;
case SR_CONF_LIMIT_MSEC:
case SR_CONF_LIMIT_SAMPLES:
- return sr_sw_limits_config_get(&devc->cfg_limits, key, data);
-#if ASIX_SIGMA_WITH_TRIGGER
+ return sr_sw_limits_config_get(&devc->limit.config, key, data);
case SR_CONF_CAPTURE_RATIO:
*data = g_variant_new_uint64(devc->capture_ratio);
break;
-#endif
default:
return SR_ERR_NA;
}
struct dev_context *devc;
int ret;
uint64_t want_rate, have_rate;
+ int idx;
(void)cg;
g_free(text_want);
g_free(text_have);
}
- devc->samplerate = have_rate;
+ devc->clock.samplerate = have_rate;
+ break;
+ case SR_CONF_EXTERNAL_CLOCK:
+ devc->clock.use_ext_clock = g_variant_get_boolean(data);
+ break;
+ case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+ idx = std_str_idx(data, ARRAY_AND_SIZE(channel_names));
+ if (idx < 0)
+ return SR_ERR_ARG;
+ devc->clock.clock_pin = idx;
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges));
+ if (idx < 0)
+ return SR_ERR_ARG;
+ devc->clock.clock_edge = idx;
break;
case SR_CONF_LIMIT_MSEC:
case SR_CONF_LIMIT_SAMPLES:
- return sr_sw_limits_config_set(&devc->cfg_limits, key, data);
-#if ASIX_SIGMA_WITH_TRIGGER
+ return sr_sw_limits_config_set(&devc->limit.config, key, data);
case SR_CONF_CAPTURE_RATIO:
devc->capture_ratio = g_variant_get_uint64(data);
break;
-#endif
default:
return SR_ERR_NA;
}
case SR_CONF_SAMPLERATE:
*data = sigma_get_samplerates_list();
break;
-#if ASIX_SIGMA_WITH_TRIGGER
+ case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+ *data = g_variant_new_strv(ARRAY_AND_SIZE(channel_names));
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges));
+ break;
case SR_CONF_TRIGGER_MATCH:
*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
break;
-#endif
default:
return SR_ERR_NA;
}
struct dev_context *devc;
uint16_t pindis_mask;
uint8_t async, div;
- int triggerpin, ret;
+ int ret;
+ size_t triggerpin;
uint8_t trigsel2;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
- uint8_t regval, trgconf_bytes[2], clock_bytes[4], *wrptr;
- size_t count;
+ uint8_t regval, cmd_bytes[4], *wrptr;
devc = sdi->priv;
+ /* Convert caller's trigger spec to driver's internal format. */
+ ret = sigma_convert_trigger(sdi);
+ if (ret != SR_OK) {
+ sr_err("Could not configure triggers.");
+ return ret;
+ }
+
/*
* Setup the device's samplerate from the value which up to now
* just got checked and stored. As a byproduct this can pick and
*
* Determine an acquisition timeout from optionally configured
* sample count or time limits. Which depends on the samplerate.
+ * Force 50MHz samplerate when external clock is in use.
*/
+ if (devc->clock.use_ext_clock) {
+ if (devc->clock.samplerate != SR_MHZ(50))
+ sr_info("External clock, forcing 50MHz samplerate.");
+ devc->clock.samplerate = SR_MHZ(50);
+ }
ret = sigma_set_samplerate(sdi);
if (ret != SR_OK)
return ret;
if (ret != SR_OK)
return ret;
- ret = sigma_convert_trigger(sdi);
- if (ret != SR_OK) {
- sr_err("Could not configure triggers.");
- return ret;
- }
-
/* Enter trigger programming mode. */
- ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x20);
+ trigsel2 = TRGSEL2_RESET;
+ ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2);
if (ret != SR_OK)
return ret;
trigsel2 = 0;
- if (devc->samplerate >= SR_MHZ(100)) {
+ if (devc->clock.samplerate >= SR_MHZ(100)) {
/* 100 and 200 MHz mode. */
/* TODO Decipher the 0x81 magic number's purpose. */
ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81);
/* Find which pin to trigger on from mask. */
for (triggerpin = 0; triggerpin < 8; triggerpin++) {
- if (devc->trigger.risingmask & (1 << triggerpin))
+ if (devc->trigger.risingmask & BIT(triggerpin))
break;
- if (devc->trigger.fallingmask & (1 << triggerpin))
+ if (devc->trigger.fallingmask & BIT(triggerpin))
break;
}
if (devc->trigger.fallingmask)
trigsel2 |= TRGSEL2_PINPOL_RISE;
- } else if (devc->samplerate <= SR_MHZ(50)) {
+ } else if (devc->clock.samplerate <= SR_MHZ(50)) {
/* 50MHz firmware modes. */
/* Translate application specs to hardware perspective. */
/* Setup trigger in and out pins to default values. */
memset(&triggerinout_conf, 0, sizeof(triggerinout_conf));
- triggerinout_conf.trgout_bytrigger = 1;
- triggerinout_conf.trgout_enable = 1;
+ triggerinout_conf.trgout_bytrigger = TRUE;
+ triggerinout_conf.trgout_enable = TRUE;
/* TODO
* Verify the correctness of this implementation. The previous
* version used to assign to a C language struct with bit fields
* Which means that I could not verify "on paper" either. Let's
* re-visit this code later during research for trigger support.
*/
- wrptr = trgconf_bytes;
+ wrptr = cmd_bytes;
regval = 0;
if (triggerinout_conf.trgout_bytrigger)
regval |= TRGOPT_TRGOOUTEN;
if (triggerinout_conf.trgout_enable)
regval |= TRGOPT_TRGOEN;
write_u8_inc(&wrptr, regval);
- count = wrptr - trgconf_bytes;
ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION,
- trgconf_bytes, count);
+ cmd_bytes, wrptr - cmd_bytes);
if (ret != SR_OK)
return ret;
* Derive a mask where bits are set for unavailable channels.
* Either send the single byte, or the full byte sequence.
*/
- pindis_mask = ~((1UL << devc->num_channels) - 1);
- if (devc->samplerate > SR_MHZ(50)) {
+ pindis_mask = ~BITS_MASK(devc->interp.num_channels);
+ if (devc->clock.samplerate > SR_MHZ(50)) {
ret = sigma_set_register(devc, WRITE_CLOCK_SELECT,
pindis_mask & 0xff);
} else {
- wrptr = clock_bytes;
+ wrptr = cmd_bytes;
/* Select 50MHz base clock, and divider. */
async = 0;
- div = SR_MHZ(50) / devc->samplerate - 1;
- /*
- * TODO Optionally use external clock.
- * async[0] = 1 to enable external clock
- * div[5] = 1 to select falling edge
- * div[4] = 1 to select rising edge
- * div[3:0] = 1..16 to select clock pin
- */
+ div = SR_MHZ(50) / devc->clock.samplerate - 1;
+ if (devc->clock.use_ext_clock) {
+ async = CLKSEL_CLKSEL8;
+ div = devc->clock.clock_pin + 1;
+ switch (devc->clock.clock_edge) {
+ case SIGMA_CLOCK_EDGE_RISING:
+ div |= CLKSEL_RISING;
+ break;
+ case SIGMA_CLOCK_EDGE_FALLING:
+ div |= CLKSEL_FALLING;
+ break;
+ case SIGMA_CLOCK_EDGE_EITHER:
+ div |= CLKSEL_RISING;
+ div |= CLKSEL_FALLING;
+ break;
+ }
+ }
write_u8_inc(&wrptr, async);
write_u8_inc(&wrptr, div);
write_u16be_inc(&wrptr, pindis_mask);
ret = sigma_write_register(devc, WRITE_CLOCK_SELECT,
- clock_bytes, wrptr - clock_bytes);
+ cmd_bytes, wrptr - cmd_bytes);
}
if (ret != SR_OK)
return ret;
/* Start acqusition. */
regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
-#if ASIX_SIGMA_WITH_TRIGGER
- regval |= WMR_TRGEN;
-#endif
+ if (devc->use_triggers)
+ regval |= WMR_TRGEN;
ret = sigma_set_register(devc, WRITE_MODE, regval);
if (ret != SR_OK)
return ret;
if (ret != SR_OK)
return ret;
- devc->state.state = SIGMA_CAPTURE;
+ devc->state = SIGMA_CAPTURE;
return SR_OK;
}
* already. The detour is required to have sample data retrieved
* for forced acquisition stops.
*/
- if (devc->state.state == SIGMA_CAPTURE) {
- devc->state.state = SIGMA_STOPPING;
+ if (devc->state == SIGMA_CAPTURE) {
+ devc->state = SIGMA_STOPPING;
} else {
- devc->state.state = SIGMA_IDLE;
+ devc->state = SIGMA_IDLE;
(void)sr_session_source_remove(sdi->session, -1);
}
projects / libsigrok.git / blobdiff