* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
+ * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
static int dev_clear(const struct sr_dev_driver *di)
{
- return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper);
+ return std_dev_clear_with_callback(di,
+ (std_dev_clear_callback)clear_helper);
}
static gboolean bus_addr_in_devices(int bus, int addr, GSList *devs)
static gboolean known_vid_pid(const struct libusb_device_descriptor *des)
{
+ gboolean is_sigma, is_omega;
+
if (des->idVendor != USB_VENDOR_ASIX)
return FALSE;
- if (des->idProduct != USB_PRODUCT_SIGMA && des->idProduct != USB_PRODUCT_OMEGA)
+ is_sigma = des->idProduct == USB_PRODUCT_SIGMA;
+ is_omega = des->idProduct == USB_PRODUCT_OMEGA;
+ if (!is_sigma && !is_omega)
return FALSE;
return TRUE;
}
devc->id.type = dev_type;
devc->samplerate = samplerates[0];
sr_sw_limits_init(&devc->cfg_limits);
- devc->cur_firmware = -1;
+ devc->firmware_idx = SIGMA_FW_NONE;
devc->capture_ratio = 50;
devc->use_triggers = 0;
}
case SR_CONF_DEVICE_OPTIONS:
if (cg)
return SR_ERR_NA;
- return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
+ return STD_CONFIG_LIST(key, data, sdi, cg,
+ scanopts, drvopts, devopts);
case SR_CONF_SAMPLERATE:
*data = std_gvar_samplerates(samplerates, samplerates_count);
break;
uint8_t triggerselect;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
- uint8_t regval;
- uint8_t clock_bytes[sizeof(clockselect)];
- size_t clock_idx;
+ uint8_t regval, trgconf_bytes[2], clock_bytes[4], *wrptr;
+ size_t count;
devc = sdi->priv;
}
/* Enter trigger programming mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT2, 0x20, devc);
+ sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x20);
triggerselect = 0;
if (devc->samplerate >= SR_MHZ(100)) {
/* 100 and 200 MHz mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT2, 0x81, devc);
+ sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81);
/* Find which pin to trigger on from mask. */
- for (triggerpin = 0; triggerpin < 8; triggerpin++)
- if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
- (1 << triggerpin))
+ for (triggerpin = 0; triggerpin < 8; triggerpin++) {
+ if (devc->trigger.risingmask & (1 << triggerpin))
+ break;
+ if (devc->trigger.fallingmask & (1 << triggerpin))
break;
+ }
/* Set trigger pin and light LED on trigger. */
- triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
+ triggerselect = TRGSEL2_LEDSEL1 | (triggerpin & 0x7);
/* Default rising edge. */
if (devc->trigger.fallingmask)
} else if (devc->samplerate <= SR_MHZ(50)) {
/* All other modes. */
- sigma_build_basic_trigger(&lut, devc);
+ sigma_build_basic_trigger(devc, &lut);
- sigma_write_trigger_lut(&lut, devc);
+ sigma_write_trigger_lut(devc, &lut);
- triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
+ triggerselect = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0;
}
/* Setup trigger in and out pins to default values. */
memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
triggerinout_conf.trgout_bytrigger = 1;
triggerinout_conf.trgout_enable = 1;
-
- sigma_write_register(WRITE_TRIGGER_OPTION,
- (uint8_t *) &triggerinout_conf,
- sizeof(struct triggerinout), devc);
-
- /* Go back to normal mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT2, triggerselect, devc);
+ /* TODO
+ * Verify the correctness of this implementation. The previous
+ * version used to assign to a C language struct with bit fields
+ * which is highly non-portable and hard to guess the resulting
+ * raw memory layout or wire transfer content. The C struct's
+ * field names did not match the vendor documentation's names.
+ * Which means that I could not verify "on paper" either. Let's
+ * re-visit this code later during research for trigger support.
+ */
+ wrptr = trgconf_bytes;
+ regval = 0;
+ if (triggerinout_conf.trgout_bytrigger)
+ regval |= TRGOPT_TRGOOUTEN;
+ write_u8_inc(&wrptr, regval);
+ regval &= ~TRGOPT_CLEAR_MASK;
+ if (triggerinout_conf.trgout_enable)
+ regval |= TRGOPT_TRGOEN;
+ write_u8_inc(&wrptr, regval);
+ count = wrptr - trgconf_bytes;
+ sigma_write_register(devc, WRITE_TRIGGER_OPTION, trgconf_bytes, count);
+
+ /* Leave trigger programming mode. */
+ sigma_set_register(devc, WRITE_TRIGGER_SELECT2, triggerselect);
/* Set clock select register. */
clockselect.async = 0;
- clockselect.fraction = 1 - 1; /* Divider 1. */
+ clockselect.fraction = 1; /* Divider 1. */
clockselect.disabled_channels = 0x0000; /* All channels enabled. */
if (devc->samplerate == SR_MHZ(200)) {
/* Enable 4 channels. */
- clockselect.disabled_channels = 0xf0ff;
+ clockselect.disabled_channels = 0xfff0;
} else if (devc->samplerate == SR_MHZ(100)) {
/* Enable 8 channels. */
- clockselect.disabled_channels = 0x00ff;
+ clockselect.disabled_channels = 0xff00;
} else {
/*
* 50 MHz mode, or fraction thereof. The 50MHz reference
* (The driver lists a discrete set of sample rates, but
* all of them fit the above description.)
*/
- clockselect.fraction = SR_MHZ(50) / devc->samplerate - 1;
+ clockselect.fraction = SR_MHZ(50) / devc->samplerate;
}
- clock_idx = 0;
- clock_bytes[clock_idx++] = clockselect.async;
- clock_bytes[clock_idx++] = clockselect.fraction;
- clock_bytes[clock_idx++] = clockselect.disabled_channels & 0xff;
- clock_bytes[clock_idx++] = clockselect.disabled_channels >> 8;
- sigma_write_register(WRITE_CLOCK_SELECT, clock_bytes, clock_idx, devc);
+ wrptr = clock_bytes;
+ write_u8_inc(&wrptr, clockselect.async);
+ write_u8_inc(&wrptr, clockselect.fraction - 1);
+ write_u16be_inc(&wrptr, clockselect.disabled_channels);
+ count = wrptr - clock_bytes;
+ sigma_write_register(devc, WRITE_CLOCK_SELECT, clock_bytes, count);
/* Setup maximum post trigger time. */
- sigma_set_register(WRITE_POST_TRIGGER,
- (devc->capture_ratio * 255) / 100, devc);
+ sigma_set_register(devc, WRITE_POST_TRIGGER,
+ (devc->capture_ratio * 255) / 100);
/* Start acqusition. */
- regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
+ regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
#if ASIX_SIGMA_WITH_TRIGGER
regval |= WMR_TRGEN;
#endif
- sigma_set_register(WRITE_MODE, regval, devc);
+ sigma_set_register(devc, WRITE_MODE, regval);
std_session_send_df_header(sdi);
/* Add capture source. */
- sr_session_source_add(sdi->session, -1, 0, 10, sigma_receive_data, (void *)sdi);
+ sr_session_source_add(sdi->session, -1, 0, 10,
+ sigma_receive_data, (void *)sdi);
devc->state.state = SIGMA_CAPTURE;