static void clear_helper(struct dev_context *devc)
{
- ftdi_deinit(&devc->ftdic);
+ (void)sigma_force_close(devc);
}
static int dev_clear(const struct sr_dev_driver *di)
devc->id.serno = serno_num;
devc->id.prefix = serno_pre;
devc->id.type = dev_type;
- devc->samplerate = samplerates[0];
sr_sw_limits_init(&devc->cfg_limits);
- devc->firmware_idx = SIGMA_FW_NONE;
devc->capture_ratio = 50;
devc->use_triggers = 0;
+
+ /* TODO Retrieve some of this state from hardware? */
+ devc->firmware_idx = SIGMA_FW_NONE;
+ devc->samplerate = sigma_get_samplerate(sdi);
}
libusb_free_device_list(devlist, 1);
g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
static int dev_open(struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- long vid, pid;
- const char *serno;
- int ret;
devc = sdi->priv;
sr_err("OMEGA support is not implemented yet.");
return SR_ERR_NA;
}
- vid = devc->id.vid;
- pid = devc->id.pid;
- serno = sdi->serial_num;
-
- ret = ftdi_init(&devc->ftdic);
- if (ret < 0) {
- sr_err("Cannot initialize FTDI context (%d): %s.",
- ret, ftdi_get_error_string(&devc->ftdic));
- return SR_ERR_IO;
- }
- ret = ftdi_usb_open_desc_index(&devc->ftdic, vid, pid, NULL, serno, 0);
- if (ret < 0) {
- sr_err("Cannot open device (%d): %s.",
- ret, ftdi_get_error_string(&devc->ftdic));
- return SR_ERR_IO;
- }
- return SR_OK;
+ return sigma_force_open(sdi);
}
static int dev_close(struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- int ret;
devc = sdi->priv;
- ret = ftdi_usb_close(&devc->ftdic);
- ftdi_deinit(&devc->ftdic);
-
- return (ret == 0) ? SR_OK : SR_ERR;
+ return sigma_force_close(devc);
}
static int config_get(uint32_t key, GVariant **data,
return STD_CONFIG_LIST(key, data, sdi, cg,
scanopts, drvopts, devopts);
case SR_CONF_SAMPLERATE:
- *data = std_gvar_samplerates(samplerates, samplerates_count);
+ *data = sigma_get_samplerates_list();
break;
#if ASIX_SIGMA_WITH_TRIGGER
case SR_CONF_TRIGGER_MATCH:
static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- struct clockselect_50 clockselect;
+ uint16_t pindis_mask;
+ uint8_t async, div;
int triggerpin, ret;
- uint8_t triggerselect;
+ uint8_t trigsel2;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
uint8_t regval, trgconf_bytes[2], clock_bytes[4], *wrptr;
if (ret != SR_OK)
return ret;
- triggerselect = 0;
+ trigsel2 = 0;
if (devc->samplerate >= SR_MHZ(100)) {
/* 100 and 200 MHz mode. */
+ /* TODO Decipher the 0x81 magic number's purpose. */
ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81);
if (ret != SR_OK)
return ret;
}
/* Set trigger pin and light LED on trigger. */
- triggerselect = TRGSEL2_LEDSEL1 | (triggerpin & 0x7);
+ trigsel2 = triggerpin & TRGSEL2_PINS_MASK;
+ trigsel2 |= TRGSEL2_LEDSEL1;
/* Default rising edge. */
+ /* TODO Documentation disagrees, bit set means _rising_ edge. */
if (devc->trigger.fallingmask)
- triggerselect |= 1 << 3;
+ trigsel2 |= TRGSEL2_PINPOL_RISE;
} else if (devc->samplerate <= SR_MHZ(50)) {
- /* All other modes. */
+ /* 50MHz firmware modes. */
+
+ /* Translate application specs to hardware perspective. */
ret = sigma_build_basic_trigger(devc, &lut);
if (ret != SR_OK)
return ret;
+ /* Communicate resulting register values to the device. */
ret = sigma_write_trigger_lut(devc, &lut);
if (ret != SR_OK)
return ret;
- triggerselect = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0;
+ trigsel2 = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0;
}
/* Setup trigger in and out pins to default values. */
return ret;
/* Leave trigger programming mode. */
- ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, triggerselect);
+ ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2);
if (ret != SR_OK)
return ret;
- /* Set clock select register. */
- clockselect.async = 0;
- clockselect.fraction = 1; /* Divider 1. */
- clockselect.disabled_channels = 0x0000; /* All channels enabled. */
- if (devc->samplerate == SR_MHZ(200)) {
- /* Enable 4 channels. */
- clockselect.disabled_channels = 0xfff0;
- } else if (devc->samplerate == SR_MHZ(100)) {
- /* Enable 8 channels. */
- clockselect.disabled_channels = 0xff00;
+ /*
+ * Samplerate dependent clock and channels configuration. Some
+ * channels by design are not available at higher clock rates.
+ * Register layout differs between firmware variants (depth 1
+ * with LSB channel mask above 50MHz, depth 4 with more details
+ * up to 50MHz).
+ *
+ * Derive a mask where bits are set for unavailable channels.
+ * Either send the single byte, or the full byte sequence.
+ */
+ pindis_mask = ~((1UL << devc->num_channels) - 1);
+ if (devc->samplerate > SR_MHZ(50)) {
+ ret = sigma_set_register(devc, WRITE_CLOCK_SELECT,
+ pindis_mask & 0xff);
} else {
+ wrptr = clock_bytes;
+ /* Select 50MHz base clock, and divider. */
+ async = 0;
+ div = SR_MHZ(50) / devc->samplerate - 1;
/*
- * 50 MHz mode, or fraction thereof. The 50MHz reference
- * can get divided by any integer in the range 1 to 256.
- * Divider minus 1 gets written to the hardware.
- * (The driver lists a discrete set of sample rates, but
- * all of them fit the above description.)
+ * TODO Optionally use external clock.
+ * async[0] = 1 to enable external clock
+ * div[5] = 1 to select falling edge
+ * div[4] = 1 to select rising edge
+ * div[3:0] = 1..16 to select clock pin
*/
- clockselect.fraction = SR_MHZ(50) / devc->samplerate;
+ write_u8_inc(&wrptr, async);
+ write_u8_inc(&wrptr, div);
+ write_u16be_inc(&wrptr, pindis_mask);
+ ret = sigma_write_register(devc, WRITE_CLOCK_SELECT,
+ clock_bytes, wrptr - clock_bytes);
}
- wrptr = clock_bytes;
- write_u8_inc(&wrptr, clockselect.async);
- write_u8_inc(&wrptr, clockselect.fraction - 1);
- write_u16be_inc(&wrptr, clockselect.disabled_channels);
- count = wrptr - clock_bytes;
- ret = sigma_write_register(devc, WRITE_CLOCK_SELECT, clock_bytes, count);
if (ret != SR_OK)
return ret;
projects / libsigrok.git / blobdiff