static int samples_per_event = 0;
static uint64_t supported_samplerates[] = {
+ KHZ(250),
+ MHZ(1),
+ MHZ(10),
+ MHZ(25),
MHZ(50),
MHZ(100),
MHZ(200),
};
static struct samplerates samplerates = {
- MHZ(50),
+ KHZ(250),
MHZ(200),
0,
supported_samplerates,
"asix-sigma-phasor.fw", /* Frequency counter */
};
-static int sigma_read(void* buf, size_t size)
+static int sigma_read(void *buf, size_t size)
{
int ret;
break;
}
- /* Prepare firmware */
+ /* Prepare firmware. */
snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
firmware_files[firmware_idx]);
g_free(buf);
if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
- g_warning("ftdi_set_bitmode failed: %s",
+ g_warning("ftdi_set_bitmode failed: %s",
ftdi_get_error_string(&ftdic));
return SIGROK_ERR;
}
struct sigrok_device_instance *sdi;
int ret;
- /* Make sure it's an ASIX SIGMA */
+ /* Make sure it's an ASIX SIGMA. */
if ((ret = ftdi_usb_open_desc(&ftdic,
USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
if (samplerate <= MHZ(50)) {
ret = upload_firmware(0);
num_probes = 16;
- // XXX: Setup divider
+ // XXX: Setup divider if < 50 MHz
}
if (samplerate == MHZ(100)) {
ret = upload_firmware(1);
info = sdi;
break;
case DI_NUM_PROBES:
- info = GINT_TO_POINTER(4);
+ info = GINT_TO_POINTER(16);
break;
case DI_SAMPLERATES:
info = &samplerates;
/* For each probe. */
for (l = 0; l < num_probes; ++l)
- cur_sample |= (!!(event[j] &
- (1 << (l * 2 + k)))) << l;
+ cur_sample |= (!!(event[j] & (1 << (l *
+ samples_per_event + k))))
+ << l;
samples[n++] = cur_sample;
}
struct datafeed_packet packet;
struct datafeed_header header;
uint8_t trigger_option[2] = { 0x38, 0x00 };
+ struct clockselect_50 clockselect;
+ int frac;
session_device_id = session_device_id;
device_index = device_index;
- if (cur_firmware == -1) {
- /* Samplerate has not been set. Default to 200 MHz */
+ /* If the samplerate has not been set, default to 200 MHz. */
+ if (cur_firmware == -1)
set_samplerate(sdi, 200);
- }
/* Setup trigger (by trigger-in). */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
/* Trigger normal (falling edge). */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08);
- /* Enable pins (200 MHz, 4 pins). */
- sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
+ /* Set clock select register. */
+ if (cur_samplerate == MHZ(200))
+ /* Enable 4 probes. */
+ sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
+ else if (cur_samplerate == MHZ(100))
+ /* Enable 8 probes. */
+ sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
+ else {
+ /*
+ * 50 MHz mode (or fraction thereof). Any fraction down to
+ * 50 MHz / 256 can be used, but is not suppoted by sigrok API.
+ */
+ frac = MHZ(50) / cur_samplerate - 1;
+
+ clockselect.async = 0;
+ clockselect.fraction = frac;
+ clockselect.disabled_probes = 0;
+
+ sigma_write_register(WRITE_CLOCK_SELECT,
+ (uint8_t *) &clockselect,
+ sizeof(clockselect));
+ }
/* Setup maximum post trigger time. */
sigma_set_register(WRITE_POST_TRIGGER, 0xff);
gettimeofday(&header.starttime, NULL);
header.samplerate = cur_samplerate;
header.protocol_id = PROTO_RAW;
- header.num_probes = 4;
+ header.num_probes = num_probes;
session_bus(session_device_id, &packet);
return SIGROK_OK;
hw_get_capabilities,
hw_set_configuration,
hw_start_acquisition,
- hw_stop_acquisition
+ hw_stop_acquisition,
};