/*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrok project.
*
* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
#define USB_DESCRIPTION "ASIX SIGMA"
#define USB_VENDOR_NAME "ASIX"
#define USB_MODEL_NAME "SIGMA"
-#define USB_MODEL_VERSION ""
#define TRIGGER_TYPE "rf10"
-#define NUM_PROBES 16
SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
static struct sr_dev_driver *di = &asix_sigma_driver_info;
-static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
-
-static const uint64_t supported_samplerates[] = {
- SR_KHZ(200),
- SR_KHZ(250),
- SR_KHZ(500),
- SR_MHZ(1),
- SR_MHZ(5),
- SR_MHZ(10),
- SR_MHZ(25),
- SR_MHZ(50),
- SR_MHZ(100),
- SR_MHZ(200),
- 0,
+static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
+
+/*
+ * The ASIX Sigma supports arbitrary integer frequency divider in
+ * the 50MHz mode. The divider is in range 1...256 , allowing for
+ * very precise sampling rate selection. This driver supports only
+ * a subset of the sampling rates.
+ */
+static const uint64_t samplerates[] = {
+ SR_KHZ(200), /* div=250 */
+ SR_KHZ(250), /* div=200 */
+ SR_KHZ(500), /* div=100 */
+ SR_MHZ(1), /* div=50 */
+ SR_MHZ(5), /* div=10 */
+ SR_MHZ(10), /* div=5 */
+ SR_MHZ(25), /* div=2 */
+ SR_MHZ(50), /* div=1 */
+ SR_MHZ(100), /* Special FW needed */
+ SR_MHZ(200), /* Special FW needed */
};
/*
- * Probe numbers seem to go from 1-16, according to this image:
+ * Channel numbers seem to go from 1-16, according to this image:
* http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
* (the cable has two additional GND pins, and a TI and TO pin)
*/
-static const char *probe_names[NUM_PROBES + 1] = {
+static const char *channel_names[] = {
"1", "2", "3", "4", "5", "6", "7", "8",
"9", "10", "11", "12", "13", "14", "15", "16",
- NULL,
-};
-
-static const struct sr_samplerates samplerates = {
- .low = 0,
- .high = 0,
- .step = 0,
- .list = supported_samplerates,
};
-static const int hwcaps[] = {
+static const int32_t hwcaps[] = {
SR_CONF_LOGIC_ANALYZER,
SR_CONF_SAMPLERATE,
+ SR_CONF_TRIGGER_TYPE,
SR_CONF_CAPTURE_RATIO,
-
SR_CONF_LIMIT_MSEC,
- 0,
-};
-
-/* Force the FPGA to reboot. */
-static uint8_t suicide[] = {
- 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
-};
-
-/* Prepare to upload firmware (FPGA specific). */
-static uint8_t init[] = {
- 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ SR_CONF_LIMIT_SAMPLES,
};
/* Initialize the logic analyzer mode. */
0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
};
-static const char *firmware_files[] = {
- "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
- "asix-sigma-100.fw", /* 100 MHz */
- "asix-sigma-200.fw", /* 200 MHz */
- "asix-sigma-50sync.fw", /* Synchronous clock from pin */
- "asix-sigma-phasor.fw", /* Frequency counter */
+static const char *sigma_firmware_files[] = {
+ /* 50 MHz, supports 8 bit fractions */
+ FIRMWARE_DIR "/asix-sigma-50.fw",
+ /* 100 MHz */
+ FIRMWARE_DIR "/asix-sigma-100.fw",
+ /* 200 MHz */
+ FIRMWARE_DIR "/asix-sigma-200.fw",
+ /* Synchronous clock from pin */
+ FIRMWARE_DIR "/asix-sigma-50sync.fw",
+ /* Frequency counter */
+ FIRMWARE_DIR "/asix-sigma-phasor.fw",
};
static int sigma_read(void *buf, size_t size, struct dev_context *devc)
return SR_OK;
}
-static int clear_instances(void)
+static void clear_helper(void *priv)
{
- GSList *l;
- struct sr_dev_inst *sdi;
- struct drv_context *drvc;
struct dev_context *devc;
- drvc = di->priv;
+ devc = priv;
- /* Properly close all devices. */
- for (l = drvc->instances; l; l = l->next) {
- if (!(sdi = l->data)) {
- /* Log error, but continue cleaning up the rest. */
- sr_err("%s: sdi was NULL, continuing", __func__);
- continue;
- }
- if (sdi->priv) {
- devc = sdi->priv;
- ftdi_free(&devc->ftdic);
- }
- sr_dev_inst_free(sdi);
- }
- g_slist_free(drvc->instances);
- drvc->instances = NULL;
+ ftdi_deinit(&devc->ftdic);
+}
- return SR_OK;
+static int dev_clear(void)
+{
+ return std_dev_clear(di, clear_helper);
}
-static int hw_init(struct sr_context *sr_ctx)
+static int init(struct sr_context *sr_ctx)
{
- return std_hw_init(sr_ctx, di, DRIVER_LOG_DOMAIN);
+ return std_init(sr_ctx, di, LOG_PREFIX);
}
-static GSList *hw_scan(GSList *options)
+static GSList *scan(GSList *options)
{
struct sr_dev_inst *sdi;
- struct sr_probe *probe;
+ struct sr_channel *ch;
struct drv_context *drvc;
struct dev_context *devc;
GSList *devices;
struct ftdi_device_list *devlist;
char serial_txt[10];
uint32_t serial;
- int ret, i;
+ int ret;
+ unsigned int i;
(void)options;
devices = NULL;
- clear_instances();
-
if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
sr_err("%s: devc malloc failed", __func__);
return NULL;
devc->period_ps = 0;
devc->limit_msec = 0;
devc->cur_firmware = -1;
- devc->num_probes = 0;
+ devc->num_channels = 0;
devc->samples_per_event = 0;
devc->capture_ratio = 50;
devc->use_triggers = 0;
/* Register SIGMA device. */
if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
- USB_MODEL_NAME, USB_MODEL_VERSION))) {
+ USB_MODEL_NAME, NULL))) {
sr_err("%s: sdi was NULL", __func__);
goto free;
}
sdi->driver = di;
- for (i = 0; probe_names[i]; i++) {
- if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
- probe_names[i])))
+ for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
+ ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
+ channel_names[i]);
+ if (!ch)
return NULL;
- sdi->probes = g_slist_append(sdi->probes, probe);
+ sdi->channels = g_slist_append(sdi->channels, ch);
}
devices = g_slist_append(devices, sdi);
return NULL;
}
-static GSList *hw_dev_list(void)
+static GSList *dev_list(void)
{
- struct drv_context *drvc;
+ return ((struct drv_context *)(di->priv))->instances;
+}
- drvc = di->priv;
+/*
+ * Configure the FPGA for bitbang mode.
+ * This sequence is documented in section 2. of the ASIX Sigma programming
+ * manual. This sequence is necessary to configure the FPGA in the Sigma
+ * into Bitbang mode, in which it can be programmed with the firmware.
+ */
+static int sigma_fpga_init_bitbang(struct dev_context *devc)
+{
+ uint8_t suicide[] = {
+ 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+ };
+ uint8_t init_array[] = {
+ 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01,
+ };
+ int i, ret, timeout = 10000;
+ uint8_t data;
+
+ /* Section 2. part 1), do the FPGA suicide. */
+ sigma_write(suicide, sizeof(suicide), devc);
+ sigma_write(suicide, sizeof(suicide), devc);
+ sigma_write(suicide, sizeof(suicide), devc);
+ sigma_write(suicide, sizeof(suicide), devc);
+
+ /* Section 2. part 2), do pulse on D1. */
+ sigma_write(init_array, sizeof(init_array), devc);
+ ftdi_usb_purge_buffers(&devc->ftdic);
- return drvc->instances;
+ /* Wait until the FPGA asserts D6/INIT_B. */
+ for (i = 0; i < timeout; i++) {
+ ret = sigma_read(&data, 1, devc);
+ if (ret < 0)
+ return ret;
+ /* Test if pin D6 got asserted. */
+ if (data & (1 << 5))
+ return 0;
+ /* The D6 was not asserted yet, wait a bit. */
+ usleep(10000);
+ }
+
+ return SR_ERR_TIMEOUT;
}
static int upload_firmware(int firmware_idx, struct dev_context *devc)
unsigned char pins;
size_t buf_size;
unsigned char result[32];
- char firmware_path[128];
+ const char *firmware = sigma_firmware_files[firmware_idx];
+ struct ftdi_context *ftdic = &devc->ftdic;
/* Make sure it's an ASIX SIGMA. */
- if ((ret = ftdi_usb_open_desc(&devc->ftdic,
- USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
+ ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
+ USB_DESCRIPTION, NULL);
+ if (ret < 0) {
sr_err("ftdi_usb_open failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ ftdi_get_error_string(ftdic));
return 0;
}
- if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
+ ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
+ if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ ftdi_get_error_string(ftdic));
return 0;
}
/* Four times the speed of sigmalogan - Works well. */
- if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
+ ret = ftdi_set_baudrate(ftdic, 750000);
+ if (ret < 0) {
sr_err("ftdi_set_baudrate failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ ftdi_get_error_string(ftdic));
return 0;
}
- /* Force the FPGA to reboot. */
- sigma_write(suicide, sizeof(suicide), devc);
- sigma_write(suicide, sizeof(suicide), devc);
- sigma_write(suicide, sizeof(suicide), devc);
- sigma_write(suicide, sizeof(suicide), devc);
-
- /* Prepare to upload firmware (FPGA specific). */
- sigma_write(init, sizeof(init), devc);
-
- ftdi_usb_purge_buffers(&devc->ftdic);
-
- /* Wait until the FPGA asserts INIT_B. */
- while (1) {
- ret = sigma_read(result, 1, devc);
- if (result[0] & 0x20)
- break;
- }
+ /* Initialize the FPGA for firmware upload. */
+ ret = sigma_fpga_init_bitbang(devc);
+ if (ret)
+ return ret;
/* Prepare firmware. */
- snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
- firmware_files[firmware_idx]);
-
- if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
+ ret = bin2bitbang(firmware, &buf, &buf_size);
+ if (ret != SR_OK) {
sr_err("An error occured while reading the firmware: %s",
- firmware_path);
+ firmware);
return ret;
}
/* Upload firmare. */
- sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
+ sr_info("Uploading firmware file '%s'.", firmware);
sigma_write(buf, buf_size, devc);
g_free(buf);
- if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
+ ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
+ if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ ftdi_get_error_string(ftdic));
return SR_ERR;
}
- ftdi_usb_purge_buffers(&devc->ftdic);
+ ftdi_usb_purge_buffers(ftdic);
/* Discard garbage. */
while (1 == sigma_read(&pins, 1, devc))
return SR_OK;
}
-static int hw_dev_open(struct sr_dev_inst *sdi)
+static int dev_open(struct sr_dev_inst *sdi)
{
struct dev_context *devc;
int ret;
static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
{
- int i, ret;
- struct dev_context *devc = sdi->priv;
+ struct dev_context *devc;
+ unsigned int i;
+ int ret;
+ devc = sdi->priv;
ret = SR_OK;
- for (i = 0; supported_samplerates[i]; i++) {
- if (supported_samplerates[i] == samplerate)
+ for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
+ if (samplerates[i] == samplerate)
break;
}
- if (supported_samplerates[i] == 0)
+ if (samplerates[i] == 0)
return SR_ERR_SAMPLERATE;
if (samplerate <= SR_MHZ(50)) {
ret = upload_firmware(0, devc);
- devc->num_probes = 16;
+ devc->num_channels = 16;
}
if (samplerate == SR_MHZ(100)) {
ret = upload_firmware(1, devc);
- devc->num_probes = 8;
+ devc->num_channels = 8;
}
else if (samplerate == SR_MHZ(200)) {
ret = upload_firmware(2, devc);
- devc->num_probes = 4;
+ devc->num_channels = 4;
}
devc->cur_samplerate = samplerate;
devc->period_ps = 1000000000000ULL / samplerate;
- devc->samples_per_event = 16 / devc->num_probes;
+ devc->samples_per_event = 16 / devc->num_channels;
devc->state.state = SIGMA_IDLE;
return ret;
/*
* In 100 and 200 MHz mode, only a single pin rising/falling can be
* set as trigger. In other modes, two rising/falling triggers can be set,
- * in addition to value/mask trigger for any number of probes.
+ * in addition to value/mask trigger for any number of channels.
*
* The Sigma supports complex triggers using boolean expressions, but this
* has not been implemented yet.
*/
-static int configure_probes(const struct sr_dev_inst *sdi)
+static int configure_channels(const struct sr_dev_inst *sdi)
{
struct dev_context *devc = sdi->priv;
- const struct sr_probe *probe;
+ const struct sr_channel *ch;
const GSList *l;
int trigger_set = 0;
- int probebit;
+ int channelbit;
memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
- for (l = sdi->probes; l; l = l->next) {
- probe = (struct sr_probe *)l->data;
- probebit = 1 << (probe->index);
+ for (l = sdi->channels; l; l = l->next) {
+ ch = (struct sr_channel *)l->data;
+ channelbit = 1 << (ch->index);
- if (!probe->enabled || !probe->trigger)
+ if (!ch->enabled || !ch->trigger)
continue;
if (devc->cur_samplerate >= SR_MHZ(100)) {
"200MHz mode is supported.");
return SR_ERR;
}
- if (probe->trigger[0] == 'f')
- devc->trigger.fallingmask |= probebit;
- else if (probe->trigger[0] == 'r')
- devc->trigger.risingmask |= probebit;
+ if (ch->trigger[0] == 'f')
+ devc->trigger.fallingmask |= channelbit;
+ else if (ch->trigger[0] == 'r')
+ devc->trigger.risingmask |= channelbit;
else {
sr_err("Only rising/falling trigger in 100 "
"and 200MHz mode is supported.");
++trigger_set;
} else {
/* Simple trigger support (event). */
- if (probe->trigger[0] == '1') {
- devc->trigger.simplevalue |= probebit;
- devc->trigger.simplemask |= probebit;
+ if (ch->trigger[0] == '1') {
+ devc->trigger.simplevalue |= channelbit;
+ devc->trigger.simplemask |= channelbit;
}
- else if (probe->trigger[0] == '0') {
- devc->trigger.simplevalue &= ~probebit;
- devc->trigger.simplemask |= probebit;
+ else if (ch->trigger[0] == '0') {
+ devc->trigger.simplevalue &= ~channelbit;
+ devc->trigger.simplemask |= channelbit;
}
- else if (probe->trigger[0] == 'f') {
- devc->trigger.fallingmask |= probebit;
+ else if (ch->trigger[0] == 'f') {
+ devc->trigger.fallingmask |= channelbit;
++trigger_set;
}
- else if (probe->trigger[0] == 'r') {
- devc->trigger.risingmask |= probebit;
+ else if (ch->trigger[0] == 'r') {
+ devc->trigger.risingmask |= channelbit;
++trigger_set;
}
return SR_OK;
}
-static int hw_dev_close(struct sr_dev_inst *sdi)
+static int dev_close(struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- if (!(devc = sdi->priv)) {
- sr_err("%s: sdi->priv was NULL", __func__);
- return SR_ERR_BUG;
- }
+ devc = sdi->priv;
/* TODO */
if (sdi->status == SR_ST_ACTIVE)
return SR_OK;
}
-static int hw_cleanup(void)
+static int cleanup(void)
{
- if (!di->priv)
- return SR_OK;
-
- clear_instances();
-
- return SR_OK;
+ return dev_clear();
}
-static int config_get(int id, const void **data, const struct sr_dev_inst *sdi)
+static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
+ const struct sr_channel_group *cg)
{
struct dev_context *devc;
+ (void)cg;
+
switch (id) {
case SR_CONF_SAMPLERATE:
if (sdi) {
devc = sdi->priv;
- *data = &devc->cur_samplerate;
+ *data = g_variant_new_uint64(devc->cur_samplerate);
} else
return SR_ERR;
break;
default:
- return SR_ERR_ARG;
+ return SR_ERR_NA;
}
return SR_OK;
}
-static int config_set(int id, const void *value, const struct sr_dev_inst *sdi)
+static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
+ const struct sr_channel_group *cg)
{
struct dev_context *devc;
+ uint64_t num_samples;
int ret;
+ (void)cg;
+
+ if (sdi->status != SR_ST_ACTIVE)
+ return SR_ERR_DEV_CLOSED;
+
devc = sdi->priv;
- if (id == SR_CONF_SAMPLERATE) {
- ret = set_samplerate(sdi, *(const uint64_t *)value);
- } else if (id == SR_CONF_LIMIT_MSEC) {
- devc->limit_msec = *(const uint64_t *)value;
+ switch (id) {
+ case SR_CONF_SAMPLERATE:
+ ret = set_samplerate(sdi, g_variant_get_uint64(data));
+ break;
+ case SR_CONF_LIMIT_MSEC:
+ devc->limit_msec = g_variant_get_uint64(data);
if (devc->limit_msec > 0)
ret = SR_OK;
else
ret = SR_ERR;
- } else if (id == SR_CONF_CAPTURE_RATIO) {
- devc->capture_ratio = *(const uint64_t *)value;
+ break;
+ case SR_CONF_LIMIT_SAMPLES:
+ num_samples = g_variant_get_uint64(data);
+ devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
+ break;
+ case SR_CONF_CAPTURE_RATIO:
+ devc->capture_ratio = g_variant_get_uint64(data);
if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
ret = SR_ERR;
else
ret = SR_OK;
- } else {
- ret = SR_ERR;
+ break;
+ default:
+ ret = SR_ERR_NA;
}
return ret;
}
-static int config_list(int key, const void **data, const struct sr_dev_inst *sdi)
+static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
+ const struct sr_channel_group *cg)
{
+ GVariant *gvar;
+ GVariantBuilder gvb;
(void)sdi;
+ (void)cg;
switch (key) {
case SR_CONF_DEVICE_OPTIONS:
- *data = hwcaps;
+ *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
+ hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
break;
case SR_CONF_SAMPLERATE:
- *data = &samplerates;
+ g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
+ gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
+ ARRAY_SIZE(samplerates), sizeof(uint64_t));
+ g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
+ *data = g_variant_builder_end(&gvb);
break;
case SR_CONF_TRIGGER_TYPE:
- *data = (char *)TRIGGER_TYPE;
+ *data = g_variant_new_string(TRIGGER_TYPE);
break;
default:
- return SR_ERR_ARG;
+ return SR_ERR_NA;
}
return SR_OK;
logic.length = tosend * sizeof(uint16_t);
logic.unitsize = 2;
logic.data = samples + sent;
- sr_session_send(devc->session_dev_id, &packet);
+ sr_session_send(devc->cb_data, &packet);
sent += tosend;
}
for (k = 0; k < devc->samples_per_event; ++k) {
cur_sample = 0;
- /* For each probe. */
- for (l = 0; l < devc->num_probes; ++l)
+ /* For each channel. */
+ for (l = 0; l < devc->num_channels; ++l)
cur_sample |= (!!(event[j] & (1 << (l *
devc->samples_per_event + k)))) << l;
logic.length = tosend * sizeof(uint16_t);
logic.unitsize = 2;
logic.data = samples;
- sr_session_send(devc->session_dev_id, &packet);
+ sr_session_send(devc->cb_data, &packet);
sent += tosend;
}
/* Only send trigger if explicitly enabled. */
if (devc->use_triggers) {
packet.type = SR_DF_TRIGGER;
- sr_session_send(devc->session_dev_id, &packet);
+ sr_session_send(devc->cb_data, &packet);
}
}
logic.length = tosend * sizeof(uint16_t);
logic.unitsize = 2;
logic.data = samples + sent;
- sr_session_send(devc->session_dev_id, &packet);
+ sr_session_send(devc->cb_data, &packet);
}
*lastsample = samples[n - 1];
return SR_OK;
}
-static int receive_data(int fd, int revents, void *cb_data)
+static void download_capture(struct sr_dev_inst *sdi)
{
- struct sr_dev_inst *sdi = cb_data;
- struct dev_context *devc = sdi->priv;
- struct sr_datafeed_packet packet;
+ struct dev_context *devc;
const int chunks_per_read = 32;
unsigned char buf[chunks_per_read * CHUNK_SIZE];
- int bufsz, numchunks, i, newchunks;
+ int bufsz, i, numchunks, newchunks;
+
+ sr_info("Downloading sample data.");
+
+ devc = sdi->priv;
+ devc->state.chunks_downloaded = 0;
+ numchunks = (devc->state.stoppos + 511) / 512;
+ newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
+
+ bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
+ /* TODO: Check bufsz. For now, just avoid compiler warnings. */
+ (void)bufsz;
+
+ /* Find first ts. */
+ if (devc->state.chunks_downloaded == 0) {
+ devc->state.lastts = RL16(buf) - 1;
+ devc->state.lastsample = 0;
+ }
+
+ /* Decode chunks and send them to sigrok. */
+ for (i = 0; i < newchunks; ++i) {
+ int limit_chunk = 0;
+
+ /* The last chunk may potentially be only in part. */
+ if (devc->state.chunks_downloaded == numchunks - 1) {
+ /* Find the last valid timestamp */
+ limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
+ }
+
+ if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
+ decode_chunk_ts(buf + (i * CHUNK_SIZE),
+ &devc->state.lastts,
+ &devc->state.lastsample,
+ devc->state.triggerpos & 0x1ff,
+ limit_chunk, sdi);
+ else
+ decode_chunk_ts(buf + (i * CHUNK_SIZE),
+ &devc->state.lastts,
+ &devc->state.lastsample,
+ -1, limit_chunk, sdi);
+
+ ++devc->state.chunks_downloaded;
+ }
+
+}
+
+static int receive_data(int fd, int revents, void *cb_data)
+{
+ struct sr_dev_inst *sdi;
+ struct dev_context *devc;
+ struct sr_datafeed_packet packet;
uint64_t running_msec;
struct timeval tv;
+ int numchunks;
+ uint8_t modestatus;
(void)fd;
(void)revents;
+ sdi = cb_data;
+ devc = sdi->priv;
+
/* Get the current position. */
sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
- numchunks = (devc->state.stoppos + 511) / 512;
-
if (devc->state.state == SIGMA_IDLE)
return TRUE;
if (devc->state.state == SIGMA_CAPTURE) {
+ numchunks = (devc->state.stoppos + 511) / 512;
+
/* Check if the timer has expired, or memory is full. */
gettimeofday(&tv, 0);
running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
(tv.tv_usec - devc->start_tv.tv_usec) / 1000;
if (running_msec < devc->limit_msec && numchunks < 32767)
- return TRUE; /* While capturing... */
- else
- hw_dev_acquisition_stop(sdi, sdi);
-
- }
-
- if (devc->state.state == SIGMA_DOWNLOAD) {
- if (devc->state.chunks_downloaded >= numchunks) {
- /* End of samples. */
- packet.type = SR_DF_END;
- sr_session_send(devc->session_dev_id, &packet);
-
- devc->state.state = SIGMA_IDLE;
-
+ /* Still capturing. */
return TRUE;
- }
- newchunks = MIN(chunks_per_read,
- numchunks - devc->state.chunks_downloaded);
+ /* Stop acquisition. */
+ sigma_set_register(WRITE_MODE, 0x11, devc);
- sr_info("Downloading sample data: %.0f %%.",
- 100.0 * devc->state.chunks_downloaded / numchunks);
+ /* Set SDRAM Read Enable. */
+ sigma_set_register(WRITE_MODE, 0x02, devc);
- bufsz = sigma_read_dram(devc->state.chunks_downloaded,
- newchunks, buf, devc);
- /* TODO: Check bufsz. For now, just avoid compiler warnings. */
- (void)bufsz;
+ /* Get the current position. */
+ sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
- /* Find first ts. */
- if (devc->state.chunks_downloaded == 0) {
- devc->state.lastts = *(uint16_t *) buf - 1;
- devc->state.lastsample = 0;
- }
+ /* Check if trigger has fired. */
+ modestatus = sigma_get_register(READ_MODE, devc);
+ if (modestatus & 0x20)
+ devc->state.triggerchunk = devc->state.triggerpos / 512;
+ else
+ devc->state.triggerchunk = -1;
- /* Decode chunks and send them to sigrok. */
- for (i = 0; i < newchunks; ++i) {
- int limit_chunk = 0;
+ /* Transfer captured data from device. */
+ download_capture(sdi);
- /* The last chunk may potentially be only in part. */
- if (devc->state.chunks_downloaded == numchunks - 1) {
- /* Find the last valid timestamp */
- limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
- }
+ /* All done. */
+ packet.type = SR_DF_END;
+ sr_session_send(sdi, &packet);
- if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
- decode_chunk_ts(buf + (i * CHUNK_SIZE),
- &devc->state.lastts,
- &devc->state.lastsample,
- devc->state.triggerpos & 0x1ff,
- limit_chunk, sdi);
- else
- decode_chunk_ts(buf + (i * CHUNK_SIZE),
- &devc->state.lastts,
- &devc->state.lastsample,
- -1, limit_chunk, sdi);
-
- ++devc->state.chunks_downloaded;
- }
+ dev_acquisition_stop(sdi, sdi);
}
return TRUE;
{
int i, j, k, bit;
- /* For each quad probe. */
+ /* For each quad channel. */
for (i = 0; i < 4; ++i) {
entry[i] = 0xffff;
/* For each bit in LUT. */
for (j = 0; j < 16; ++j)
- /* For each probe in quad. */
+ /* For each channel in quad. */
for (k = 0; k < 4; ++k) {
bit = 1 << (i * 4 + k);
return SR_OK;
}
-static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
- void *cb_data)
+static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
{
struct dev_context *devc;
- struct sr_datafeed_packet *packet;
- struct sr_datafeed_header *header;
struct clockselect_50 clockselect;
int frac, triggerpin, ret;
uint8_t triggerselect = 0;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
+ if (sdi->status != SR_ST_ACTIVE)
+ return SR_ERR_DEV_CLOSED;
+
devc = sdi->priv;
- if (configure_probes(sdi) != SR_OK) {
- sr_err("Failed to configure probes.");
+ if (configure_channels(sdi) != SR_OK) {
+ sr_err("Failed to configure channels.");
return SR_ERR;
}
/* Set clock select register. */
if (devc->cur_samplerate == SR_MHZ(200))
- /* Enable 4 probes. */
+ /* Enable 4 channels. */
sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
else if (devc->cur_samplerate == SR_MHZ(100))
- /* Enable 8 probes. */
+ /* Enable 8 channels. */
sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
else {
/*
clockselect.async = 0;
clockselect.fraction = frac;
- clockselect.disabled_probes = 0;
+ clockselect.disabled_channels = 0;
sigma_write_register(WRITE_CLOCK_SELECT,
(uint8_t *) &clockselect,
gettimeofday(&devc->start_tv, 0);
sigma_set_register(WRITE_MODE, 0x0d, devc);
- devc->session_dev_id = cb_data;
-
- if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
- sr_err("%s: packet malloc failed.", __func__);
- return SR_ERR_MALLOC;
- }
-
- if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
- sr_err("%s: header malloc failed.", __func__);
- return SR_ERR_MALLOC;
- }
+ devc->cb_data = cb_data;
/* Send header packet to the session bus. */
- packet->type = SR_DF_HEADER;
- packet->payload = header;
- header->feed_version = 1;
- gettimeofday(&header->starttime, NULL);
- sr_session_send(devc->session_dev_id, packet);
+ std_session_send_df_header(cb_data, LOG_PREFIX);
/* Add capture source. */
sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
- g_free(header);
- g_free(packet);
-
devc->state.state = SIGMA_CAPTURE;
return SR_OK;
}
-static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
+static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
{
struct dev_context *devc;
- uint8_t modestatus;
(void)cb_data;
- sr_source_remove(0);
-
- if (!(devc = sdi->priv)) {
- sr_err("%s: sdi->priv was NULL", __func__);
- return SR_ERR_BUG;
- }
-
- /* Stop acquisition. */
- sigma_set_register(WRITE_MODE, 0x11, devc);
-
- /* Set SDRAM Read Enable. */
- sigma_set_register(WRITE_MODE, 0x02, devc);
-
- /* Get the current position. */
- sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
-
- /* Check if trigger has fired. */
- modestatus = sigma_get_register(READ_MODE, devc);
- if (modestatus & 0x20)
- devc->state.triggerchunk = devc->state.triggerpos / 512;
- else
- devc->state.triggerchunk = -1;
-
- devc->state.chunks_downloaded = 0;
+ devc = sdi->priv;
+ devc->state.state = SIGMA_IDLE;
- devc->state.state = SIGMA_DOWNLOAD;
+ sr_source_remove(0);
return SR_OK;
}
.name = "asix-sigma",
.longname = "ASIX SIGMA/SIGMA2",
.api_version = 1,
- .init = hw_init,
- .cleanup = hw_cleanup,
- .scan = hw_scan,
- .dev_list = hw_dev_list,
- .dev_clear = clear_instances,
+ .init = init,
+ .cleanup = cleanup,
+ .scan = scan,
+ .dev_list = dev_list,
+ .dev_clear = dev_clear,
.config_get = config_get,
.config_set = config_set,
.config_list = config_list,
- .dev_open = hw_dev_open,
- .dev_close = hw_dev_close,
- .dev_acquisition_start = hw_dev_acquisition_start,
- .dev_acquisition_stop = hw_dev_acquisition_stop,
+ .dev_open = dev_open,
+ .dev_close = dev_close,
+ .dev_acquisition_start = dev_acquisition_start,
+ .dev_acquisition_stop = dev_acquisition_stop,
.priv = NULL,
};
projects / libsigrok.git / blobdiff