/*
- * This file is part of the fx2lafw project.
+ * This file is part of the sigrok-firmware-fx2lafw project.
*
* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
#include <fx2lafw.h>
#include <gpif-acquisition.h>
-bit gpif_acquiring;
+__bit gpif_acquiring;
static void gpif_reset_waveforms(void)
{
/* When GPIF is idle, tri-state the data bus. */
/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
- GPIFIDLECS = (1 << 0);
+ GPIFIDLECS = (0 << 0);
/* When GPIF is idle, set CTL0-CTL5 to 0. */
GPIFIDLECTL = 0;
/* Contains RDY* pin values. Read-only according to TRM. */
GPIFREADYSTAT = 0;
- /* Make GPIF stop on transcation count not flag */
+ /* Make GPIF stop on transaction count not flag. */
EP2GPIFPFSTOP = (0 << 0);
}
/* Initialize flowstate registers (not used by us). */
gpif_init_flowstates();
- /* Reset the status */
+ /* Reset the status. */
gpif_acquiring = FALSE;
}
-static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay)
+static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t opcode, uint8_t output)
{
/*
* DELAY
* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
* Collect data in this state.
*/
- pSTATE[8] = 0x00;
+ pSTATE[8] = opcode;
/*
* OUTPUT
* OE[0:3]=0, CTL[0:3]=0
*/
- pSTATE[16] = 0x00;
+ pSTATE[16] = output;
/*
* LOGIC FUNCTION
/* Ensure GPIF is idle before reconfiguration. */
while (!(GPIFTRIG & 0x80));
+ /* Configure the EP2 FIFO. */
+ if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) {
+ EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
+ } else {
+ EP2FIFOCFG = bmAUTOIN;
+ }
+ SYNCDELAY();
+
/* Set IFCONFIG to the correct clock source. */
if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
bmGSTATE | bmIFGPIF;
}
- /* Populate delay states */
- if((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
- cmd->sample_delay_h >= 6)
- return false;
+ if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
+ uint8_t delay_1, delay_2;
- for(i = 0; i < cmd->sample_delay_h; i++)
- gpif_make_delay_state(pSTATE++, 0);
+ /* We need a pulse where the CTL2 pin alternates states. */
- if(cmd->sample_delay_l != 0)
- gpif_make_delay_state(pSTATE++, cmd->sample_delay_l);
+ /* Make the low pulse shorter then the high pulse. */
+ delay_2 = cmd->sample_delay_l >> 2;
+ /* Work around >12MHz case resulting in a 0 delay low pulse. */
+ if (delay_2 == 0)
+ delay_2 = 1;
+ delay_1 = cmd->sample_delay_l - delay_2;
+
+ gpif_make_delay_state(pSTATE++, delay_2, 0x00, 0x40);
+ gpif_make_delay_state(pSTATE++, delay_1, 0x00, 0x44);
+ } else {
+ /* Populate delay states. */
+ if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
+ cmd->sample_delay_h >= 6)
+ return false;
+
+ for (i = 0; i < cmd->sample_delay_h; i++)
+ gpif_make_delay_state(pSTATE++, 0, 0x00, 0x00);
+
+ if (cmd->sample_delay_l != 0)
+ gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00, 0x00);
+ }
/* Populate S1 - the decision point. */
gpid_make_data_dp_state(pSTATE++);